Appendix; Digidoc 80-Port Post Error Code List - CHAINTECH CT-7NJS User Manual

Appendix

Digidoc 80-Port POST Error Code List

POST (hex)
Test CMOS R/W functionality.
CF
Early chipset initialization:
-Disable shadow RAM
C0
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers.
Detect memory:
-Auto-detection of DRAM size, type and ECC.
C1
-Auto-detection of L2 cache (socket 7 or below)
Expand compressed BIOS code to DRAM.
C3
Call chipset hook to copy BIOS back to E000 & F000
C5
shadow RAM.
Expand the Xgroup codes locating in physical address
01
1000:0
Initial Superio_Early_Init switch.
03
3. Blank out screen.
05
4. Clear CMOS error flag.
1. Clear 8042 interface.
07
2. Initialize 8042 self-test.
1. Test special keyboard controller for Winbond 977 series
08 Super I/O chips.
2. Enable keyboard interface.
1. Disable PS/2 mouse interface (optional).
2. Auto detects ports for keyboard & mouse followed by a
0A
port & interface swap (optional).
3. Reset keyboard for Winbond 977 series Super I/O chips.
Test F000h segment shadow to see whether it is R/W-able
0E
or not. If test fails, keep beeping the speaker.
Auto detect flash type to load appropriate flash R/W codes
10
into the run time area in F000 for ESCD & DMI support.
Use walking 1's algorithm to check out interface in CMOS
12 circuitry. Also set real-time clock power status, and then
check for override.
Appendix
Digidoc 80-Port POST Error Code List
Description
67
Digidoc 80-Port POST Error Code List
POST (hex)
Program chipset default values into chipset. Chipset
14
default values are MODBINable by OEM customers.
16 Initial Early_Init_Onboard_Generator switch.
Detect CPU information including brand, SMI type (Cyrix
18
or Intel) and CPU level (586 or 686).
Initial interrupts vector table. If no special specified, all
1B H/W interrupts are directed to SPURIOUS_INT_HDLR &
S/W interrupts to SPURIOUS_soft_HDLR.
1D Initial EARLY_PM_INIT switch.
1F Load keyboard matrix (notebook platform).
21 HPM initialization (notebook platform)
1. Check validity of RTC value: e.g. a value of 5Ah is an
invalid value for RTC minute.
2. Load CMOS settings into BIOS stack. If CMOS
checksum fails, use default value instead.
3. Prepare BIOS resource map for PCI & PnP use. If ESCD
is valid, take into consideration of the ESCD's legacy
information.
23 4. Onboard clock
respective clock resource to empty PCI & DIMM
slots.
5. Early PCI initialization:
- Enumerate PCI bus number.
- Assign memory & I/O resource.
- Search for a valid VGA device & VGA BIOS, and put it
into C000:0.
27 Initialize INT 09 buffer.
1. Program CPU internal MTRR (P6 & PII) for 0-640K
memory address.
2. Initialize the APIC for Pentium class CPU.
29 3. Program early chipset according to CMOS setup.
Example: onboard IDE controller.
4. Measure CPU speed.
5. Invoke video BIOS.
68
Appendix
Description
generator initialization. Disable