Appendix; Digidoc 80-Port Post Error Code List - CHAINTECH 9EJS1 User Manual

Appendix

Digidoc 80-Port POST Error Code List

POST (hex) Description
CF Test CMOS R/W functionality.
Early chipset initialization:
-Disable shadow RAM
C0
-Disable L2 cache (socket 7 or below)
-Program basic chipset registers.
Detect memory:
C1 -Auto-detection of DRAM size, type and ECC.
-Auto-detection of L2 cache (socket 7 or below)
Expand compressed BIOS code to DRAM.
C3
Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.
C5
Expand the Xgroup codes locating in physical address 1000:0
01
03 Initial Superio_Early_Init switch.
Blank out screen.
05
Clear CMOS error flag.
Clear 8042 interface.
07
Initialize 8042 self-test.
Test special keyboard controller for Winbond 977 series Super I/O
chips.
08
Enable keyboard interface.
Disable PS/2 mouse interface (optional).
Auto detects ports for keyboard & mouse followed by a port & interface
0A
swap (optional).
Reset keyboard for Winbond 977 series Super I/O chips.
Test F000h segment shadow to see whether it is R/W-able or not. If test
0E
fails, keep beeping the speaker.
Auto detect flash type to load appropriate flash R/W codes into the run
10
time area in F000 for ESCD & DMI support.
Use walking 1's algorithm to check out interface in CMOS circuitry.
12
Also set real-time clock power status, and then check for override.
Program chipset default values into chipset. Chipset default values are
14
MODBINable by OEM customers.
Appendix
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Appendix
16 Initial Early_Init_Onboard_Generator switch.
Detect CPU information including brand, SMI type (Cyrix or Intel®)
18
and CPU level (586 or 686).
Initial interrupts vector table. If no special specified, all
1B H/W interrupts are directed to SPURIOUS_INT_HDLR & S/W
interrupts to SPURIOUS_soft_HDLR.
1D Initial EARLY_PM_INIT switch.
1F Load keyboard matrix (notebook platform).
HPM initialization (notebook platform)
21
1. Check validity of RTC value: e.g. a value of 5Ah is an invalid
value for RTC minute.
2. Load CMOS settings into BIOS stack. If CMOS checksum fails,
use default value instead.
3. Prepare BIOS resource map for PCI & PnP use. If ESCD is
valid, take into consideration of the ESCD's legacy information.
23
4. Onboard clock generator initialization. Disable respective clock
resource to empty PCI & DIMM slots.
5. Early PCI initialization:
- Enumerate PCI bus number.
- Assign memory & I/O resource.
- Search for a valid VGA device & VGA BIOS, and put it into C000:0.
Initialize INT 09 buffer.
27
1. Program CPU internal MTRR (P6 & PII) for 0-640K memory
address.
2. Initialize the APIC for Pentium class CPU.
29 3. Program early chipset according to CMOS setup. Example:
onboard IDE controller.
4. Measure CPU speed.
5. Invoke video BIOS.
1. Initialize multi-language.
2D 2. Put information on screen display, including Award title, CPU
type, and CPU speed.
Reset keyboard except Winbond 977 series Super I/O chips.
33
3C Test 8254
3E Test 8259 interrupt mask bits for channel 1.
96