Analog Devices ADT7473 Manual page 63

Table 27. Voltage Limit Registers
Register Address
0x46
0x47
0x48
0x49
1
Setting the Configuration Register 1 lock bit has no effect on these registers.
2
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit (≤ comparison).
Table 28. Temperature Limit Registers
Register Address
0x4E
0x4F
0x50
0x51
0x52
0x53
1
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock
bit has no effect on these registers.
2 High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit (≤ comparison).
Table 29. Fan Tachometer Limit Registers
Register Address
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
1
Exceeding any of the TACH limit registers by 1 indicates the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 to
indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Table 30. Register 0x55—TACH 1 Minimum High Byte (Power-On Default = 0xFF)
Bits Name R/W
<4:0> Reserved Read-only
<7:5> SCADC Read/write
1
R/W Description
Read/write V low limit.
CCP
Read/write V high limit.
CCP
Read/write V low limit.
CC
Read/write V high limit.
CC
1
R/W Description
Read/write Remote 1 temperature low limit.
Read/write Remote 1 temperature high limit.
Read/write Local temperature low limit.
Read/write Local temperature high limit.
Read/write Remote 2 temperature low limit.
Read/write Remote 2 temperature high limit.
1
R/W Description
Read/write TACH1 minimum low byte.
Read/write TACH1 minimum high byte/single-channel ADC channel select.
Read/write TACH2 minimum low byte.
Read/write TACH2 minimum high byte.
Read/write TACH3 minimum low byte.
Read/write TACH3 minimum high byte.
Read/write TACH4 minimum low byte.
Read/write TACH4 minimum high byte.
Description
These bits are reserved when Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode).
Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte.
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits are used to
select the only channel from which the ADC makes measurements. Otherwise, these bits represent
Bits <7:5> of the TACH1 minimum high byte.
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2
2
ADT7473
Power-On Default
0x00
0xFF
0x00
0xFF
Power-On Default
0x01
0xFF
0x01
0xFF
0x01
0xFF
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF