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Table 22. Register 0x37—Dynamic T
Bit
Name
R/W
<2:0>
CYR1
Read/write
Bits
000
001
010
011
100
101
110
111
<5:3>
CYL
Read/write
Bits
000
001
010
011
100
101
110
111
<7:6>
CYR2
Read/write
Bits
000
001
010
011
100
101
110
111
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 23. Maximum PWM Duty Cycle (Power-On Default = 0xFF)
Register Address
R/W
0x38
Read/write
0x39
Read/write
0x3A
Read/Write
1
These registers set the maximum PWM duty cycle of the PWM output.
2
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
3
If Bit 3 of Configuration Register 4 (0x7D) is set, then on a THERM overtemperature event, fans go to their maximum programmed PWM value as programmed here.
If Bit 3 of Configuration Register 4 (0x7D) is 0, then on a THERM overtemperature event, fans go to 100% PWM.
Control Register 2 (Power-On Default = 0x00)
MIN
Description
3-Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent T
adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring cycles. The
system has associated thermal time constants that need to be found to optimize the response of fans and
the control loop.
Decrease Cycle
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
3-Bit Local Temperature Cycle Value. These three bits define the delay time between making subsequent
T
adjustments in the control loop for the local temperature channel, in terms of number of monitoring
MIN
cycles. The system has associated thermal time constants that need to be found to optimize the response of
fans and the control loop.
Decrease Cycle
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2 LSBs of 3-Bit Remote 2 Cycle Value. The MSB of the 3-bit code resides in Dynamic T
(Reg. 0x36). These three bits define the delay time between making subsequent T
control loop for the Remote 2 channel, in terms of number of monitoring cycles. The system has associated
thermal time constants that need to be found to optimize the response of fans and the control loop.
Decrease Cycle
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2
Description
Maximum duty cycle for PWM1 output, default = 100% (0xFF).
Maximum duty cycle for PWM2 output, default = 100% (0xFF).
Maximum duty cycle for PWM3 output, default = 100% (0xFF).
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
Increase Cycle
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
1, 2, 3
Rev. 0 | Page 61 of 76
1
Control Register 1
MIN
adjustments in the
MIN
ADT7473
MIN
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