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Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts, it
is recommend handling the SMBALERT interrupt as follows:
1.
Detect the SMBALERT assertion.
2.
Enter the interrupt handler.
3.
Read the status registers to identify the interrupt source.
4.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74, Reg. 0x75).
5.
Take the appropriate action for a given interrupt source.
6.
Exit the interrupt handler.
7.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 27.
HIGH LIMIT
TEMPERATURE
STICKY
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
INTERRUPT
MASK BIT SET
Figure 27. How Masking the Interrupt Source Affects SMBALERT Output
Masking Interrupt Sources
Interrupt Mask Register 1 is located at Address 0x74; Interrupt
Mask Register 2 is located at Address 0x75. These allow
individual interrupt sources to be masked out to prevent
SMBALERT interrupts. Masking an interrupt source prevents
only the SMBALERT output from being asserted; the
appropriate status bit is set normally.
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 2 (V
) = 1, masks SMBALERT for V
CC
Bit 0 (V
) = 1, masks SMBALERT for V
CCP
CLEARED ON READ
(TEMP BELOW LIMIT)
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
channel.
CC
channel.
CCP
Rev. 0 | Page 21 of 76
Interrupt Mask Register 2 (Reg. 0x75)
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
If the TACH4 pin is being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM limits).
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default. Pin 5
or Pin 9 can be reconfigured as an SMBALERT output to signal
out-of-limit conditions.
Table 11. Configuring Pin 5 as SMBALERT Output
Register
Configuration Register 3 (Reg. 0x78)
Assigning THERM Functionality to a Pin
Pin 9 on the ADT7473 has four possible functions: SMBus
ALERT, THERM , GPIO, and TACH4. The user chooses the
required functionality by setting Bit 0 and Bit 1 of Configura-
tion Register 4 at Address 0x7D.
Bit 0
Bit 1
00
01
10
11
Once Pin 9 is configured as THERM , it must be enabled (Bit 1,
Configuration Register 3 at Address 0x78).
THERM as an Input
When THERM is configured as an input, the ADT7473 can
time assertions on the THERM pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge system
performance. See the THERM Timer section for more
information.
ADT7473
Bit Setting
<0> ALERT = 1
Function
TACH4
THERM
SMBus ALERT
GPIO
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