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ADT7473
Parameter
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, V
IH
Input Low Voltage, V
IL
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU;DAT
Detect Clock Low Timeout, t
SCL
t
HD; STA
SDA
t
BUF
P
S
Min
2.0
−0.3
10
4.7
4.7
4.0
250
15
TIMEOUT
t
t
R
F
t
LOW
t
HIGH
t
HD; DAT
Figure 2. Serial Bus Timing Diagram
Typ
Max
3.6
0.8
0.5
0.75 × V
CC
0.4
±1
±1
5
400
50
50
1,000
300
35
t
SU; STA
t
SU; DAT
S
Rev. 0 | Page 4 of 76
Unit
Test Conditions/Comments
V
V
Maximum input voltage
V
V
Minimum input voltage
V p-p
V
V
μA
V
= V
IN
CC
μA
V
= 0
IN
pF
See Figure 2
kHz
ns
μs
μs
μs
ns
μs
ns
ms
Can be optionally disabled
t
HD; STA
t
SU; STO
P
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