Figure 1-1: Timing Diagram Of The Spi Interface - Tektronix RTX130B Service Manual

Specifications
DATA 0- - 7
DCLK
PSYNC
DVALID
DATA 0- - 7
DCLK*
DATA 0- - 7
DCLK*

Figure 1-1: Timing diagram of the SPI interface

1-12
188 bytes
5 ns 5 ns
Output data delay
T/2  T/10
Input data hold time
Transition period
RTX130B QAM & VSB RF Signal Generator Service Manual
T (1/f)
T/2  T/10
Input clock pulse width