Figure A-1: Timing Diagram Of The Spi Interface - Tektronix RTX130A User Manual

DATA 0-7
DCLK
PSYNC
DVALID
DATA 0-7
DCLK
DATA 0-7
DCLK

Figure A-1: Timing diagram of the SPI interface

RTX130A QAM & VSB RF Signal Generator User Manual
188 bytes
5 ns
5 ns
Output data delay
T/2 ± T/10
Input data hold time
Transition period
Appendix A: Specifications
T (f/1)
T/2 ± T/10
Input clock pulse width
A-9