Table of Contents
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Figure 5. DSP Block Image
DSP Features
Architecture
Inputs
Filter per channel
Filter types
High- Lowpass types
FIR Filter
Delay
CurrentLimiter
Voltagelimiter
Powerlimiter
Speakerdetection
4.3. USER INTERFACES
4.3.1. DISPLAY / BUTTONS
See
and
on
FRONT VIEW
2021-10-20 | Rev. 3.7.5
FPGA based 32-bit fixed point
16 x input matrix
sine, white- pink- brown-noise
Mute, Volume, Phase
32 x EQ / Highpass / Lowpass
bell, notch, highshelf, lowshelf
6 - 48dB/Oct, Bessel, Butterworth, Linkwitz/Riley, Variable Q
2048 Tabs, ASCII file import
48000 Samples / 330m / 1000ms per channel
Threshold [Ap]
2 x Threshold [Vp], Attack, Release
Threshold [W], Attack, Release
20kHz Pilot Tone generating with Volume, Threshold, Debounce
MA32/D
Chapter 4. SOFTWARE
4.3. USER INTERFACES
4.3. USER INTERFACES | 16/60
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