Sharp SL-5500 Service Manual page 9

PC-UM10M
Name Type
nPIOW OCZ
nPIOR OCZ
nPCE 2:1 OCZ
nIOIS16 IC
nPWAIT IC
PSKTSEL OCZ
nPREG OCZ
L_DD 7:0 OCZ
L_FCLK OCZ
L_LCLK OCZ
L_PCLK OCZ
L_BIAS OCZ
TXD_C OCZ
RXD_C IC
SCLK_C OCZ
SFRM_C OCZ
UDC+ ICOCZ
UDC ICOCZ
TXD_1 OCZ
RXD_1 IC
TXD_2 OCZ
RXD_2 IC
TXD_3 OCZ
RXD_3 IC
GP 27:0 ICOCZ
SMROM_EN IC
ROM_SEL IC
PXTAL IC
PEXTAL OCZ
TXTAL IC
TEXTAL OCZ
PWR_EN OCZ
BATT_FAULT IC
VDD_FAULT IC
nRESET IC
PCMCIA I/O write. This signal is an output and is used to perform write transactions to the PCMCIA I/O
space.
PCMCIA I/O read. This signal is an output and is used to perform read transactions from the PCMCIA I/O
space.
PCMCIA card enable. These signals are output and are used to select a PCMCIA card. nPCE 2 enables
the high-byte lane and nPCE 1 enables the low-byte lane.
I/O Select 16. This signal is an input and is an acknowledgment from the PCMCIA card that it can perform
16-bit I/O data transfers.
PCMCIA wait. This signal is an input and is driven low by the PCMCIA card to extend the duration of
transfers to/from the SA-1110.
PCMCIA socket select. This signal is an output and used by external steering logic to route control,
address, and data signals to one of the PCMCIA sockets. When PSKTSEL is low, socket zero is selected.
When PSKTSEL is high, socket one is selected. This signal has the same timing as the address lines.
PCMCIA register select. This signal is an output and indicates that, on a memory transaction, the target
address is attribute space. This signal has the same timing as address.
LCD controller display data.
LCD frame clock.
LCD line clock.
LCD pixel clock.
LCD ac bias drive.
CODEC transmit.
CODEC receive.
CODEC clock.
CODEC frame signal
Serial port zero bidirectional, differential signalling pin (UDC).
Serial port zero bidirectional, differential signalling pin (UDC).
Serial port one transmit pin (UART).
Serial port one receive pin (UART).
Serial port two transmit pin (IrDA).
Serial port two receive pin (IrDA).
Serial port three transmit pin (UART).
Serial port three receive pin (UART).
General-purpose input output.
Synchronous mask ROM (SMROM) enable. This pin is used to determine if the boot ROM (static memory
bank 0) is asynchronous or synchronous. If asynchronous, boot ROM is selected (SMROM_EN = 0) and
its width is determined by the state of the ROM_SEL pin. SMROM is supported only on 32-bit data bus-
ses.
ROM select. This pin is used to configure the ROM width. It is either grounded or pulled high. If ROM_SEL
is grounded, the ROM width is 16 bits. If ROM_SEL is pulled up, the ROM width is 32 bits.
Input connection for 3.686-MHz crystal (non-CMOS threshold).
Output connection for 3.686-MHz crystal (non-CMOS level).
Input connection for 32.768-kHz crystal (non-CMOS threshold).
Output connection for 32.768-kHz crystal (non-CMOS level).
Power enable. Active high. PWR_EN enables the external VDD power supply. Deasserting it signals the
power supply that the system is going into sleep mode and that the VDD power supply should be
removed.
Battery fault. Signals the SA-1110 that the main power source is going away (battery is low or has been
removed from the system). The assertion of BATT_FAULT causes the SA-1110 to enter sleep mode. The
SA-1110 will not recognize a wake-up event while this signal is asserted.
VDD fault. Signals the SA-1110 that the main power supply is going out of regulation (shorted card is
inserted). VDD_FAULT will cause the SA-1110 to enter sleep mode. VDD_FAULT is ignored after a wake-
up event untill the power supply timer completes (approximately 10ms).
Hard reset. This active low signal is a level-sensitive input used to start the processor from a known
address. A low level will cause the current instruction to terminate abnormally, and the on-chip caches,
MMU, and write buffer to be disabled.
When nRESET is driven high, the processor will restart from address 0. nRESET must remain low until
the power supply is stable and the internal 3.686-MHz oscillator has come up to speed. While nRESET is
low, the processor will perform idle cycles.
SL-5500 HARDWARE DESCRIPTION
– 8 –
Description