Sharp SL-5500 Service Manual page 16

(2)-6. PCM AUDIO INTERFACE
(2)-6-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input level is at LOW.
• This module is not affected by pwren pin input.
• Converts audio data from Ti Audio Format generated by the SSP of
the CPU into Standard Data Format.
(2)-6-2. Block diagram
TiAudio Format
sclk
Standard Data Format
pin
lrclk
sfrm
sclk lrclk Leading
pin
Inversion Reset and trailing
CPU bus SCINV LRCRST LRCEVE
Register settings
(2)-7. AUDIO CLOCK
(2)-7-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input level is at LOW.
• When pwren pin input level is at LOW, the output of mclk and clk64fs
pins becomes LOW regardless of the register settings.
• Capable of monitoring the same signal as those from MCLK /
CLK64FS pins using the status register (04h) bit 0 (MCLK) / bit0
(CLK64FS).
(2)-7-2. Block diagram
Xout24m output pin
48KHz System
Xin24m input pin
Xout22m output pin
Xin22m input pin
CPU bus XON XSEL XEN
Register settings
(2)-8. GENERAL-PURPOSE 8-bit 2ch DAC CONTROL
SIGNAL
(2)-8-1. Outline
• The registers of this module are initialized when BATTFAULT pin input
level is at LOW.
• The operation of this module does not depend upon the input level of
the pwren pin.
Buffer of each pin:
SCL OUTPUT N-CH Open Drain 5-V withstand voltage, 2mA
SDA INPUT 5-V withstand voltage, 2mA (not a feed-through current
prevention
buffer)
(2)-8-2. Block diagram
DAC power supply ON
DO
F/F
CPU
sda
SDA
bus
DI
Input pin
F/F
scl
SDAOEB
output pin
F/F
Initialize
SCLOEB
Register settings
dacsck
output pin
lrclk
lrclk
Inversion
output pin
Initialize
battfault
LRCINV SCEN LRCEN
input pin
Internal status register
bit10(MCLK)
MCLK
Dividing
output pin
circuits
Internal register
bit*(CLK64FS)
CLK64FS
output pin
3
Initialize
CLKSEL CLK64FS battfault
MCLKEN
[2:0] EN input pin
3.3~
Power supply
F/F
5.0V
ON/OFF
LCD
1ch
sda
COMADJ
I/O pin
Backlight
voltage
2ch
scl
light
input pin
control
General-purpose
battfault 8-bit DAC
(Mitsubishi
input pin
M62332FP)
SL-5500 HARDWARE DESCRIPTION
(2)-9. TFT-RELATED SIGNAL
(2)-9-1. Outline
• The registers of this module are initialized when the BATTFAULT pin
input lever is at LOW.
• The operation of this module does not depend upon pwren pin input
level.
(2)-9-2. Block diagram
hs pin
CPS generation circuit
Delay amount
setting
CPS inversion
dclk pin
CPU
CPS[3:0] CPSOUT CPSEN
bus
Register settings
(2)-10. INTERRUPT CONTROLLER
(2)-10-1. Outline
• The registers of this module are initialized when batterfault pin input
level is LOW.
• The operation of this module does not depend upon pwren pin input
level.
(2)-10-2. Block diagram (Here is a circuit image.)
Interrupt
status
SPI
interrupt
SPIIS
Long-hour
timer
interrupt
LTIS
GPIO
interrupt
GPIOIS
Key
interrupt
KIS
CPU bus
SPIIE LTIE GPIOIE
Interrupt source allowed
– 15 –
PC-UM10M
VCC3 CPU(SA1110)
Scoop
(PCMCIA GA)
PA22
HS_PA21
D O
F/F
DCLK_PA20
CK
cps
output pin
TFT panel
tftreset
controller
REM
output pin
Initialize
TFTC battfault
RST input pin
TFT panel
KIE INTB
Interrupt status
of entire GA
LCDC
Intact
int_b
pin