Sharp SL-5500 Service Manual page 24

2-8. DAC (M62332)
(1) PIN CONNECTION DIAGRAM
AO1 1
AO2 2
N.C. 3
N.C. 4
(2) BLOCK DIAGRAM
VCC SCL
8 7
2
I C BUS TRANSCEIVER
Power-on
reset
8-bit latch 8-bit latch
8-bit upper 8-bit upper
segment R-2R segment R-2R
1
AO1 AO2
(3) PIN DESCRIPTION
Pin No. Symbol
6
SDA Serial data input pin
7
SCL Serial clock signal input pin
1
AO1 8-bit resolution D/A converter output pin
(After power is turned on, all channels are
2
AO2
reset and DAC data 00h is outputted.)
8
VCC Power supply voltage pin
5
GND GND pin
2-9. DAC (PCM1741)
(1) BLOCK DIAGRAM
BCK
Audio
LRCK
Serial
8x
Port
DATA
Over-
Enhanced
sampling
Multi-level
Digital
Filler
ML
with
Serial
Modulator
Function
MC
Control
Controller
Port
MDI
System Clock
System
Zero Detect
Clock
SCK
Manager
8 VCC
7 SCL
6 SDA
5 GND
SDA GND
6 5
Channel
decoder
2 3 4
N.C. N.C.
Functional description
VOUTL
Output Amp
and Low-pass
DAC
Filter
VCOM
Delta-
Slgma
Output Amp
DAC and Low-pass
Filter VOUTR
Power Supply
SL-5500 HARDWARE DESCRIPTION
(2) PIN CONFIGURATION
1 BCK
2 DATA
3 LRCK
4 DGND
5 VDD
6 VCC
7 VOUTL
8 VOUTR
(3) PIN ASSIGNMENTS
PIN NAME
1 BCK
2 DATA
3 LRCK
4 DGND
5 VDD
6 VCC
7 VOUTL
8 VOUTR
9 AGND
10 VCOM
11 ZEROR/ZEROA
12 ZEROL/NA
13 MD
14 MC
15 ML
16 SCK
Note: *1 Schmitt trigger input, 5V tolerant.
*2 Schmitt trigger input with internal pull-down, 5V tolerant.
– 23 –
PC-UM10M
PCM1741
SCK 16
ML 15
MC 14
MD 13
ZEROL/NA 12
ZEROR/ZEROA 11
VCOM 10
AGND 9
TYPE DESCRIPTIONS
IN Audio data bit clock input.
IN Audio data digital input.
IN L-channel and R-channel Audio
data latch enable input.
Digital ground.
Digital power supply, +3.3V.
Analog power supply, +3.3V
OUT Analog output for L-channel.
OUT Analog output for R-channel.
Analog ground.
Common voltage decoupling.
OUT Zero flag output for R-channel/
Zero flag output for L/R-channel.
OUT Zero flag output for
L-channel/No assign.
IN Mode control data Input.
IN Mode control clock input.
IN Mode control latch input.
IN System clock input.
*1
*1
*2
*2
*2