Sharp SL-5500 Service Manual page 18

(4) PIN FUNCTION
(4)-1. PIN DESCRIPTION BY FUNCTION (128-PIN SPECIFICATION)
Function Pin name
SA1110 BATTFAULT
interface
PWREN
( V a r i a b l e
RESET_B
Latency I/O)
RTC32K
CS_B
WE_B
OE_B
ADR[25:23]
ADR[7:2]
DATA[15:0]
Subtotal
Interrupt control INT_B
BOOT drive CS[1:0]_B
switching
MCS0[3:0]_B
circuit and
MCS1[3:0]_B
decode
FROM_B
Subtotal
Key port circuit KSTRB[7:0]
KI_B[15:0]
Subtotal
Serial output SCL
circuit for
SDA
general-purpose
Subtotal
8-bit 2ch DAC
control
TFT_C reset TFTRESET
TFT PS control CPS
AD_START ADSTART
output circuit for
HS
tablet control
DCLK
Subtotal
PWM output TIMEOUT
port
LEDPWM0
LEDPWM1
FLPWM
Subtotal
Audio XIN22M
MCLK/SCK32
output port
XOUT22M
XIN24M
XOUT24M
CLK64FS
MCLK
Subtotal
Pin No. Q'ty I/O Buffer
1 IN IBC
1 IN IBC
1 IN IBH
1 IN IBO
1 IN IBO
1 IN IBO
1 IN IBO
3 IN IBO
6 IN IBO
16 IN/OUT BA2T
32
1 OUT OB1T
2 IN IBO
4 OUT OB1T
4 OUT OB1T
1 IN IBOP2
11
8 OUT TB1HT
16 IN IBH
24
1 OUT OD1T
1 IN/OUT BG1
2
1 OUT OB1T
1 OUT OB1T
1 OUT IBO
1 IN IBO
1 IN IBO
3
1 OUT OB2T
1 OUT OB2T
1 OUT OB2T
1 OUT OB1T
4
1 IN LIN
1 OUT LOT
1 IN LIN
1 OUT LOT
1 OUT OB2T
1 OUT OB2T
6
SL-5500 HARDWARE DESCRIPTION
– 17 –
Description
Battery voltage detection input
CPU status input (L: HALT, H: Operate)
Reset input
RTC 32 kHz clock signal input
Chip selection signal for GA
Write enable signal for GA
Output enable signal for GA
Address bus
Address bus
Data bus
INT (including interrupt key) output signal
CS signal for FROM/MROM signal
MCS signal 0 for FROM/MROM decode signal
MCS signal 1 for FROM/MROM decode signal
FROM_Board detection pin
Key strobe signal
Key input signal
(external pull-up resistance is required)
Serial clock signal
Serial data
TFT_C reset signal
TFT power save CPS output signal
Tablet incorporation START signal
LCD horizontal synchronous signal
LCD data transfer clock signal
Battery charger protection timer
For charger indicator
For communication error blinking
F/L Duty light control signal (0-100%) output
44.1 KHz system base clock input
(22.5792 MHz)
44.1 KHz system base clock output
(22.5792 MHz)
48 KHz system base clock input (MHz)
48 KHz system base clock output
(22.5792 MHz)
Audio 64 fs output (SCLK x2)
Audio MCLK clock output
PC-UM10M
Connected to
Detection circuit
CPU (SA1110)
CPU (SA1110)
CPU (SA1110)
CPU (SA1110)
CPU (SA1110)
CPU (SA1110)
CPU (SA1110)
CPU (SA1110)
CPU
(SA1110 interrupt)
CPU (SA1110)
FROM/MROM
FROM/MROM
FROM/MROM
KEY_BOARD
KEY_BOARD
DAC
DAC
TFT panel
Toshiba TC35143AF
CPU
(SA1110-I, CDC)
CPU
(SA1110-I, CDC)
Charger circuit
Charger circuit
Charger circuit
F/L inverter circuit
Oscillation circuit 1
(OSC4C)
Oscillation circuit 1
(OSC4C)
Oscillation circuit 2
(OSC4C)
Oscillation circuit 2
(OSC4C)
CPU (GPI0)
Audio DAC