Sharp SL-5500 Service Manual page 7

PC-UM10M
2. DESCRIPTION OF LSI
2-1. CPU (SA-1110)
(1) GENERAL DESCRIPTION
The Intel StrongARM* SA-1110 Microprocessor (SA-1110) is a highly
integrated communications microcontroller that incorporates a 32-bit
StrongARM RISC processor core, system support logic, multiple comu-
nication channels, an LCD controller, a memory and PCMCIA controller,
and general-purpose I/O ports.
(2) FEATURES
• High Performance
– 150 Dhrystone 2.1 MIPS @ 133MHz
– 235 Dhrystone 2.1 MIPS @ 206MHz
*
• Low power (normal mode)
– <240mW @ 1.55V/133MHz
– <400mW @ 1.75V/206MHz
• Integrated clock generation
– Internal phase-locked loop (PPL)
– 3.686MHz oscillator
– 32.768kHz oscillator
• Power-management features
– Normal (full-on) mode
– Idle (power-down) mode
– Sleep (power-down) mode
• Big and little endian operating modes
• 3.3V I/O interface
• 256-pin mini-BGA package (mBGA)
• 32-way set-associative caches
– 16Kbyte instruction cache
– 8Kbyte write-back data cache
• 32-entry memory-management units
– Maps 4Kbyte, 8Kbyte, or 1Mbyte
• Write buffer
– 8-entry, between 1 and 16bytes each
• Read buffer
– 4-entry, 1, 4, or 8 words
• Memory bus
– Interfaces to ROM, synchronous mask ROM (SMROM), Flash,
SRAM, SRAM-like variable latency I/O, DRAM, and synchronous
DRAM (SDRAM)
– Supports two PCMCIA sockets
* Power dissipation, particularly in idle mode, is strongly dependent on
the details of the system design.
(3) SYSTEM CONFIGURATION
(3)-1. BLOCK DIAGRAM
3.686
OSC
MHz
32.768
OSC
KHz
RTC
OS Timer
General-
Purpose I/O
Interrupt
Controller
Power
Management
Reset
Controller
Serial
Channel 0
UDC
*Other brands and names are the property of their respective owners.
(3)-2. SA-1110 FUNCTIONAL DIAGRAM
Serial
Channel 0
(USB)
Serial
Channel 1
Serial
Channel 2
(IrDA)
Serial
Channel 3
(UART)
Serial
Channel 4
(CODEC)
BATT_FAULT
VDD_FAULT
Power
Management
Clocks,Reset
and Test
nRESET_OUT
JTAG
*Other brands and names are the property of their respective owners.
SL-5500 HARDWARE DESCRIPTION
– 6 –
Instructions
PLL1
PC
Icache
IMMU
(8 Kbytes)
ARM*
PLL2
SA-1
Addr
Dcache
DMMU Core
(8 Kbytes)
Minicache
Load/Store Data
Write Read
Buffer Buffer
System Bus
DMA
Bridge
Controller
Peripheral Bus
Serial Serial
Channel 1 Channel 2 Channel 3
GPCLK/UART IrDA
UDC- L_DD(7:0)
UDC+
L_FCLK
L_LCLK
RXD_1
L_PCLK
TXD_1
L_BIAS
RXD_2
TXD_2 GP(27:0)
Intel
RXD_3
StrongARM*
nCAS/DQM(3:0)
TXD_3
SA-1110
nRAS/nSDCS(3:0)
[256-pins]
nOE
TXD_C
nWE
RXD_C
nCS(5:0)
SCLK_C
RDY
SFRM_C
nSDRAS
nSDCAS
SDCKE<1:0>
PWR_EN
SDCLK<2:0>
RD/nWR
TCK_BYP
nPOE
TESTCLK
nPWE
PEXTAL
nPIOR
PXTAL
nPIOW
TEXTAL
nPCE<2:1>
TXTAL
PSKTSEL
nRESET
nPREG
nPWAIT
SMROM_EN
nIOIS16
ROM_SEL
TCK
TDI
TDO
VDD
TMS
VDDX
nTRST
VSS/VSSX
Intel
StrongARM*
SA-1110
Microprocessor
JTAG
and
Misc
Test
LCD
Controller
Memory and
PCMCIA
Control Module
Serial Serial
Channel 4
UART CODEC
LCD
Control
GPIO Ports
Memory
Control
Transceiver
Control
PCMCIA
Bus
Signals
Address
A<25:0>
Bus
D<31:0> Data Bus
Supply