Renesas SH7670 Series User Manual page 30

2
User Area
CS0 S29GL064A90TFIR4
<Write/Read Timing>
Write1
Th T1 Tw1 Tw2 Tw3
CKIO
tAD1
A21-A1
tCSD1
CS0#
RD#
tWED1
tAS
tCS
WE0#
tDS
tWDD1
D15-D0
Rev.1.01 2008.05.07
REJ11J0012-0101
Table 2.3.2 Bus State Controller Setting (Flash Memory Write/Read)
Target Device
CS0 space bus control register :CS0BCR
Initial value: H'36DB 0600 (at MD_BW ="L")
Recommended setting value : H'1000 0400
CS0 space wait control register: CS0WCR
Initial value: H'0000 0500
Recommended setting value : H'0000 0AC1
Tw4 Tw5 T2 Tf Taw1 Th T1 Tw1 Tw2
tWC tWC tAD1
tAD1
tCSD1
tCSD1
tWED1 tWED1
tWP tWP tCH
tAH
tWPH tWPH
tWDH1
tDH tWDD1
DATA
Figure 2.3.2 Example of Flash Memory Read/Write Access Timing
Bus State Controller Setting
• Idle cycles between write-read cycles and write-write cycles
IWW[2:0] = B'001; 1 idle cycle inserted
• Data bus specification
BSZ[1:0] = B'10 ; 16-bit bus width
• Assert delay cycle from RD# and WEn# to address and CS0#
assert
SW[1:0] = B'01; 1.5 cycles
• Number of access wait cycle
WR[3:0] = B'0110; 5 cycles
• CS0# negate delay cycle from RD# and WEn# negate to
address
HW[1:0] = B'01; 1.5 cycles
Write2
Tw3 Tw4 Tw5 T2 Tf Taw1 Th T1
tAD1
tAD1
tCSD1
tCSD1
tWED1
tAH
tAS tCH
tWP tWP tOEH
tDS tWDH1
tDH
DATA
Functional Overview
2.3.2 Flash Memory
Read1
Tw1 Tw2 Tw3 Tw4 Tw5 T2 Tf
tAD1
tRC tRC
tCSD1
tRSD tRSD
ta(OE)
ta(AD) tRDH1
ta(CE1) tRDS1 tDF(OE)
DATA
tDF(CE)
2-16