Renesas SuperH SH7600 Series Manuals

Manuals and User Guides for Renesas SuperH SH7600 Series. We have 2 Renesas SuperH SH7600 Series manuals available for free PDF download: Hardware Manual, User Manual

Renesas SuperH SH7600 Series Hardware Manual (935 pages)

32-Bit RISC Microcomputer SuperH RISC engine Family

Brand: Renesas | Category: Computer Hardware | Size: 6.19 MB

Table of Contents
11
Section 1 Overview

27
- Features of Superh Microcomputer with On-Chip Ethernet Controller
  27
- Block Diagram
  39
- Pin Description
  40
  - Pin Arrangement
    40
  - Pin Functions
    41
  - Pin Multiplexing
    47
- Processing States
  53
Section 2 CPU

57
Section 3 Oscillator Circuits and Operating Modes

133
- Overview
  133
- On-Chip Clock Pulse Generator and Operating Modes
  133
  - Clock Pulse Generator
    133
  - Clock Operating Mode Settings
    135
  - Connecting a Crystal Resonator
    138
  - External Clock Input
    139
  - Operating Frequency Selection by Register
    140
  - Clock Modes and Frequency Ranges
    148
  - Notes on Board Design
    149
- Bus Width of the CS0 Area
  150
Section 4 Exception Handling

151
- Overview
  151
- Resets
  157
  - Types of Resets
    157
  - Power-On Reset
    157
  - Manual Reset
    158
- Address Errors
  158
  - Sources of Address Errors
    158
  - Address Error Exception Handling
    160
- Interrupts
  161
  - Interrupt Sources
    161
  - Interrupt Priority Levels
    162
  - Interrupt Exception Handling
    162
- Exceptions Triggered by Instructions
  163
  - Instruction-Triggered Exception Types
    163
  - Trap Instructions
    163
  - Illegal Slot Instructions
    164
  - General Illegal Instructions
    164
- When Exception Sources Are Not Accepted
  165
- Stack Status after Exception Handling
  167
- Usage Notes
  168
Section 5 Interrupt Controller (INTC)

169
- Overview
  169
  - Features
    169
  - Block Diagram
    169
  - Pin Configuration
    171
  - Register Configuration
    171
- Interrupt Sources
  172
  - NMI Interrupt
    173
  - User Break Interrupt
    173
  - H-UDI Interrupt
    173
  - IRL Interrupts
    173
  - IRQ Interrupts
    174
  - On-Chip Peripheral Module Interrupts
    178
  - Interrupt Exception Vectors and Priority Order
    178
- Register Descriptions
  185
- Interrupt Operation
  216
  - Interrupt Sequence
    216
  - Stack State after Interrupt Exception Handling
    218
- Interrupt Response Time
  218
- Sampling of Pins IRL3-IRL0
  220
- Usage Notes
  221
Section 6 User Break Controller (UBC)

225
- Overview
  225
  - Features
    225
  - Block Diagram
    226
  - Register Configuration
    227
Appendix A On-Chip Peripheral Module Registers

227
- Addresses
  227
- Register Descriptions
  229
  - Break Address Register a (BARA)
    229
  - Break Address Mask Register a (BAMRA)
    230
  - Break Bus Cycle Register a (BBRA)
    231
  - Break Address Register B (BARB)
    233
  - Break Address Mask Register B (BAMRB)
    234
  - Break Bus Cycle Register B (BBRB)
    235
  - Break Address Register C (BARC)
    237
  - Break Address Mask Register C (BAMRC)
    238
  - Break Data Register C (BDRC)
    240
  - Break Data Mask Register C (BDMRC)
    241
  - Break Bus Cycle Register C (BBRC)
    243
  - Break Execution Times Register C (BETRC)
    244
  - Break Address Register D (BARD)
    245
  - Break Address Mask Register D (BAMRD)
    246
  - Break Data Register D (BDRD)
    248
  - Break Data Mask Register D (BDMRD)
    249
  - Break Bus Cycle Register D (BBRD)
    251
  - Break Execution Times Register D (BETRD)
    252
  - Break Control Register (BRCR)
    253
  - Branch Flag Registers (BRFR)
    259
  - Branch Source Registers (BRSR)
    260
  - Branch Destination Registers (BRDR)
    261
- Operation
  262
  - User Break Operation Sequence
    262
  - Instruction Fetch Cycle Break
    263
  - Data Access Cycle Break
    264
  - Saved Program Counter (PC) Value
    265
  - Memory Bus or y Memory Bus Cycle Break
    265
  - Sequential Break
    266
  - PC Traces
    267
  - Examples of Use
    269
  - Usage Notes
    273
Section 7 Bus State Controller (BSC)

275
- Overview
  275
  - Features
    275
  - Block Diagram
    277
  - Pin Configuration
    278
  - Register Configuration
    280
  - Address Map
    281
- Register Descriptions
  283
- Access Size and Data Alignment
  305
  - Connection to Ordinary Devices
    305
  - Connection to Little-Endian Devices
    306
- Accessing Ordinary Space
  308
  - Basic Timing
    308
  - Wait State Control
    313
  - CS Assertion Period Extension
    317
- Synchronous DRAM Interface
  318
  - Synchronous DRAM Direct Connection
    318
  - Address Multiplexing
    320
  - Burst Reads
    322
  - Single Reads
    327
  - Single Writes
    329
  - Burst Write Mode
    330
  - Bank Active Function
    332
  - Refreshes
    343
  - Overlap between Auto Precharge Cycle (Tap) and Next Access
    346
  - Power-On Sequence
    347
  - 64 Mbit Synchronous DRAM (2 Mword × × × × 32-Bit) Connection
    349
- DRAM Interface
  350
  - DRAM Direct Connection
    350
  - Address Multiplexing
    351
  - Basic Timing
    352
  - Wait State Control
    353
  - Burst Access
    355
  - EDO Mode
    358
  - DRAM Single Transfer
    362
  - Refreshing
    363
  - Power-On Sequence
    365
- Burst ROM Interface
  365
- Idles between Cycles
  369
- Bus Arbitration
  371
  - Master Mode
    375
- Additional Items
  376
  - Resets
    376
  - Access as Viewed from CPU, DMAC or E-DMAC
    377
  - STATS1 and STATS0 Pins
    378
  - Bushiz Specification
    379
- Usage Notes
  380
Section 8 Cache

383
- Introduction
  383
  - Register Configuration
    384
- Register Description
  384
  - Cache Control Register (CCR)
    384
- Address Space and the Cache
  386
- Cache Operation
  387
  - Cache Reads
    387
  - Write Access
    389
  - Cache-Through Access
    392
  - The TAS Instruction
    392
  - Pseudo-LRU and Cache Replacement
    392
  - Cache Initialization
    394
  - Associative Purges
    394
  - Cache Flushing
    395
  - Data Array Access
    395
  - Address Array Access
    396
- Cache Use
  397
  - Initialization
    397
  - Purge of Specific Lines
    398
  - Cache Data Coherency
    398
  - Two-Way Cache Mode
    399
- Usage Notes
  400
  - Standby
    400
  - Cache Control Register
    400
Section 9 Ethernet Controller (Etherc)

401
- Overview
  401
  - Features
    401
  - Configuration
    402
  - Pin Configuration
    404
  - Ethernet Controller Register Configuration
    405
- Register Descriptions
  406
- Operation
  428
  - Transmission
    428
  - Reception
    430
  - MII Frame Timing
    432
  - Accessing MII Registers
    434
  - Magic Packet Detection
    437
  - CPU Operating Mode and Ethernet Controller Operation
    438
  - CAM Match Signal Input Function
    439
- Connection to PHY-LSI
  441
Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)

443
Section 11 Direct Memory Access Controller (DMAC)

487
- Overview
  487
  - Features
    487
  - Block Diagram
    489
  - Pin Configuration
    490
  - Register Configuration
    491
- Register Descriptions
  492
- Operation
  503
  - DMA Transfer Flow
    503
  - DMA Transfer Requests
    505
  - Channel Priorities
    509
  - DMA Transfer Types
    512
  - Number of Bus Cycles
    522
  - DMA Transfer Request Acknowledge Signal Output Timing
    522
  - Dreqn Pin Input Detection Timing
    533
  - DMA Transfer End
    539
  - BH Pin Output Timing
    540
- Usage Examples
  542
  - Example of DMA Data Transfer between SCIF and External Memory
    542
- Usage Notes
  542
Section 12 16-Bit Free-Running Timer (FRT)

545
- Overview
  545
  - Features
    545
  - Block Diagram
    546
  - Pin Configuration
    547
  - Register Configuration
    547
- Register Descriptions
  548
- CPU Interface
  554
- Operation
  557
  - FRC Count Timing
    557
  - Output Timing for Output Compare
    558
  - FRC Clear Timing
    558
  - Input Capture Input Timing
    559
  - Input Capture Flag (ICF) Setting Timing
    560
  - Output Compare Flag (OCFA, OCFB) Setting Timing
    560
  - Timer Overflow Flag (OVF) Setting Timing
    561
- Interrupt Sources
  562
- Example of FRT Use
  562
- Usage Notes
  563
Section 13 Watchdog Timer (WDT)

569
- Overview
  569
  - Features
    569
  - Block Diagram
    570
  - Pin Configuration
    570
  - Register Configuration
    571
- Register Descriptions
  571
- Operation
  576
- Usage Notes
  580
Section 14 Serial Communication Interface with FIFO (SCIF)

583
- Overview
  583
  - Features
    583
  - Block Diagrams
    585
  - Pin Configuration
    586
  - Register Configuration
    587
- Register Descriptions
  588
  - Receive Shift Register (SCRSR)
    588
  - Receive FIFO Data Register (SCFRDR)
    588
  - Transmit Shift Register (SCTSR)
    589
  - Transmit FIFO Data Register (SCFTDR)
    589
  - Serial Mode Register (SCSMR)
    590
  - Serial Control Register (SCSCR)
    593
  - Serial Status 1 Register (SC1SSR)
    596
  - Serial Status 2 Register (SC2SSR)
    601
  - Bit Rate Register (SCBRR)
    604
  - FIFO Control Register (SCFCR)
    612
  - FIFO Data Count Register (SCFDR)
    614
  - FIFO Error Register (SCFER)
    615
  - Irda Mode Register (SCIMR)
    615
- Operation
  617
  - Overview
    617
  - Operation in Asynchronous Mode
    619
  - Multiprocessor Communication Function
    631
  - Operation in Synchronous Mode
    639
  - Use of Transmit/Receive FIFO Buffers
    649
  - Operation in Irda Mode
    652
- SCIF Interrupt Sources and the DMAC
  656
- Usage Notes
  657
Section 15 Serial I/O with FIFO (SIOF)

663
- Overview
  663
  - Features
    663
- Register Configuration
  665
  - Receive Shift Register (SIRSR)
    665
  - Receive Data Register (SIRDR)
    666
  - Transmit Shift Register (SITSR)
    667
  - Transmit Data Register (SITDR)
    667
  - Serial Control Register (SICTR)
    668
  - Serial Status Register (SISTR)
    671
  - Receive Control Data Register (SIRCDR)
    674
  - Transmit Control Data Register (SITCDR)
    675
  - FIFO Control Register (SIFCR)
    675
  - FIFO Data Count Register (SIFDR)
    679
- Operation
  680
  - Input When TRMD = 0 in SIFCR
    680
  - Output When TRMD = 0 in SIFCR
    683
  - Output When TRMD = 1 in SIFCR
    687
- SIOF Interrupt Sources and DMAC
  689
Section 16 Serial I/O (SIO)

691
- Overview
  691
  - Features
    691
- Register Configuration
  694
  - Receive Shift Register (SIRSR)
    695
  - Receive Data Register (SIRDR)
    695
  - Transmit Shift Register (SITSR)
    696
  - Transmit Data Register (SITDR)
    696
  - Serial Control Register (SICTR)
    697
  - Serial Status Register (SISTR)
    699
- Operation
  701
  - Input
    701
  - Output
    702
- SIO Interrupt Sources and DMAC
  705
Section 17 16-Bit Timer Pulse Unit (TPU)

707
- Overview
  707
  - Features
    707
  - Block Diagram
    710
  - Pin Configuration
    711
  - Register Configuration
    712
- Register Descriptions
  713
  - Timer Control Register (TCR)
    713
  - Timer Mode Register (TMDR)
    716
  - Timer I/O Control Register (TIOR)
    718
  - Timer Interrupt Enable Register (TIER)
    725
  - Timer Status Register (TSR)
    727
  - Timer Counter (TCNT)
    730
  - Timer General Register (TGR)
    731
  - Timer Start Register (TSTR)
    731
  - Timer Synchronous Register (TSYR)
    732
- Interface to Bus Master
  733
  - 16-Bit Registers
    733
- Operation
  735
  - Overview
    735
  - Basic Functions
    736
  - Synchronous Operation
    742
  - Buffer Operation
    744
  - PWM Modes
    747
  - Phase Counting Mode
    752
- Interrupts
  757
  - Interrupt Sources and Priorities
    757
  - DMAC Activation
    758
- Operation Timing
  759
  - Input/Output Timing
    759
  - Interrupt Signal Timing
    763
- Usage Notes
  766
- Usage Notes
  776
  - Clearing Flags in TSR0 to TSR2
    776
  - DMA Transfer by TPU0
    776
Section 18 User Debug Interface (H-UDI)

777
- Overview
  777
  - Features
    777
  - H-UDI Block Diagram
    778
  - Pin Configuration
    779
  - Register Configuration
    779
- External Signals
  780
  - Test Clock (TCK)
    780
  - Test Mode Select (TMS)
    780
  - Test Data Input (TDI)
    780
  - Test Data Output (TDO)
    781
  - Test Reset (TRST)
    781
- Register Descriptions
  781
  - Instruction Register (SDIR)
    781
  - Status Register (SDSR)
    783
  - Data Register (SDDR)
    784
  - Bypass Register (SDBPR)
    784
  - Boundary Scan Register (SDBSR)
    784
  - ID Code Register (SDIDR)
    796
- Operation
  797
  - TAP Controller
    797
  - H-UDI Interrupt and Serial Transfer
    798
  - H-UDI Reset
    801
- Boundary Scan
  801
  - Supported Instructions
    801
  - Notes on Use
    803
- Usage Notes
  803
Section 19 Pin Function Controller (PFC)

807
- Overview
  807
- Register Configuration
  809
- Register Descriptions
  809
  - Port a Control Register (PACR)
    809
  - Port a I/O Register (PAIOR)
    812
  - Port B Control Registers (PBCR, PBCR2)
    813
  - Port B I/O Register (PBIOR)
    819
Section 20 I/O Ports

821
- Overview
  821
- Port a
  821
  - Register Configuration
    822
  - Port a Data Register (PADR)
    822
- Port B
  823
  - Register Configuration
    823
  - Port B Data Register (PBDR)
    824
Section 21 Power-Down Modes

825
- Overview
  825
  - Power-Down Modes
    825
  - Register
    826
- Register Descriptions
  827
  - Standby Control Register 1 (SBYCR1)
    827
  - Standby Control Register 2 (SBYCR2)
    829
- Sleep Mode
  831
  - Transition to Sleep Mode
    831
  - Canceling Sleep Mode
    831
- Standby Mode
  831
  - Transition to Standby Mode
    831
  - Canceling Standby Mode
    833
  - Standby Mode Cancellation by NMI Interrupt
    833
  - Clock Pause Function
    834
  - Notes on Standby Mode
    837
- Module Standby Function
  838
  - Transition to Module Standby Function
    838
  - Clearing the Module Standby Function
    838
Section 22 Electrical Characteristics

839
- Absolute Maximum Ratings
  839
- DC Characteristics
  840
- AC Characteristics
  842
  - Clock Timing
    843
  - Control Signal Timing
    847
  - Bus Timing
    849
  - Direct Memory Access Controller Timing
    887
  - Free-Running Timer Timing
    888
  - Serial Communication Interface Timing
    890
  - Watchdog Timer Timing
    894
  - Serial I/O with FIFO / Serial I/O Timing
    895
  - User Debug Interface Timing
    898
  - I/O Port Timing
    899
Appendix B Pin States

926
- Pin States in Reset, Power-Down State, and Bus-Released State
  926
Appendix C Product Lineup

930
Appendix D Package Dimensions

931

Renesas SuperH SH7600 Series User Manual (38 pages)

SuperH Family E10A Emulator

Brand: Renesas | Category: Computer Hardware | Size: 0.35 MB

Renesas Categories

Computer Hardware Motherboard Microcontrollers Adapter

Switch

More Renesas Manuals

Renesas SuperH SH7600 Series Manuals

Renesas SuperH SH7600 Series Hardware Manual (935 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 Oscillator Circuits and Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller (INTC)

Section 6 User Break Controller (UBC)

Appendix A On-Chip Peripheral Module Registers

Section 7 Bus State Controller (BSC)

Section 8 Cache

Section 9 Ethernet Controller (Etherc)

Section 10 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Section 11 Direct Memory Access Controller (DMAC)

Section 12 16-Bit Free-Running Timer (FRT)

Section 13 Watchdog Timer (WDT)

Section 14 Serial Communication Interface with FIFO (SCIF)

Section 15 Serial I/O with FIFO (SIOF)

Section 16 Serial I/O (SIO)

Section 17 16-Bit Timer Pulse Unit (TPU)

Section 18 User Debug Interface (H-UDI)

Section 19 Pin Function Controller (PFC)

Section 20 I/O Ports

Section 21 Power-Down Modes

Section 22 Electrical Characteristics

Appendix B Pin States

Appendix C Product Lineup

Appendix D Package Dimensions

Renesas SuperH SH7600 Series User Manual (38 pages)

Table of Contents

Related Products

Renesas Categories