Yonah 1/2 - EUROCOM M620NC Service Manual

Yonah 1/2

U28A
4 H_A#[31:3]
H_A#3 J4 H1
A[3]# ADS#
H_A#4
L4 E2
A[4]# BNR#
H_A#5 M3 G5
A[5]# BPRI#
H_A#6 K5
A[6]#
H_A#7 M1 H5
A[7]# DEFER#
H_A#8
N2 F21
A[8]# DRDY #
H_A#9 J1 E1
A[9]# DBSY #
H_A#10 N3
A[10]#
H_A#11
P5 F1
A[11]# BR0#
H_A#12 P2
A[12]#
H_A#13 L1 D20 H_IERR#
A[13]# IERR#
H_A#14
P4 B3
A[14]# INIT#
H_A#15
P1
A[15]#
H_A#16 R1 H4
A[16]# LOCK#
L2
4 H_ADSTB#0
ADSTB[0]#
B1
4 H_REQ#[4:0] RESET#
H_REQ#0 K3 F3
REQ[0]# RS[0]#
H_REQ#1 H2 F4
REQ[1]# RS[1]#
H_REQ#2
K2 G3
REQ[2]# RS[2]#
H_REQ#3
J3 G2
REQ[3]# TRDY #
H_REQ#4 L5
REQ[4]#
G6
4 H_A#[31:3]
HIT#
H_A#17
Y2 E4
A[17]# HITM#
H_A#18 U5
A[18]#
H_A#19 R3 AD4 H_BPM0#
A[19]# BPM[0]#
H_A#20 H_BPM1#
W6 AD3
A[20]# BPM[1]#
H_A#21 H_BPM2#
U4 AD1
A[21]# BPM[2]#
H_A#22 Y5 AC4 H_BPM3#
A[22]# BPM[3]#
H_A#23 U2 AC2 H_PRDY #
A[23]# PRDY #
H_A#24 H_PREQ#
R4 AC1
A[24]# PREQ#
H_A#25 T5 AC5 H_TCK
A[25]# TCK
H_A#26 T3 AA6 H_TDI
A[26]# TDI
H_A#27 W3 AB3 H_TDO
A[27]# TDO
H_A#28 H_TMS
W5 AB5
A[28]# TMS
H_A#29 Y4 AB6 H_TRST#
A[29]# TRST#
H_A#30 W2 C20 ITP_DBRST#
A[30]# DBR#
H_A#31
Y1
A[31]#
V4 D21 H_PROCHOT#
4 H_ADSTB#1
ADSTB[1]# PROCHOT
A24 H_THERMDA
THERMDA
A6 A25 H_THERMDC
14 H_A20M# A20M# THERMDC
A5
14 H_FERR# FERR#
C4 C7
14 H_IGNNE#
IGNNE# THERMTRIP#
D5
14 H_STPCLK# STPCLK#
C6
14 H_INTR
LINT0
B4 A22
14 H_NMI
LINT1 BCLK[0]
A3 A21
14 H_SMI# SMI# BCLK[1]
Z0201 AA1 A2 TZ0202
RSVD[01]# NC
Z0202 AA4 T22 Z0212
RSVD[02]# RSVD[12]#
Z0203
AB2
RSVD[03]#
Z0204 AA3
RSVD[04]#
Z0205 M4 D2 Z0213
RSVD[05]# RSVD[13]#
Z0206 N5 F6 Z0214
RSVD[06]# RSVD[14]#
Z0207 Z0215
T2 D3
RSVD[07]# RSVD[15]#
Z0208 V3 C1 Z0216
RSVD[08]# RSVD[16]#
Z0209 B2 AF1 Z0217
RSVD[09]# RSVD[17]#
Z0210 Z0218
C3 D22
RSVD[10]# RSVD[18]#
C23 Z0219
RSVD[19]#
Z0211 B25 C24 Z0220
RSVD[11]# RSVD[20]#
CPU
+1.05VS
R83 56_04 H_IERR#
R339 54.9_1%_04 H_PREQ#
R335 39_1%_04 H_TMS
Layout Note:
H_TDI
R333 150_1%_04
Within 2.0" of the CPU
R338 27_04 H_TCK
H_TRST#
R337 680_04
+H8VCC
+3VS
R84 150_1%_04 ITP_DBRST#
+1.05VS
R82 56_04 H_PROCHOT#
If PROCHOT# is not used, then it must be
23
terminated with a 56 ¡Ó5% pull-up resistor
to VCCP.The R_isolate can be placed
anywhere as long as it does not have a
stub.L1, L2 and L5 can be routed on
different layers.
If PROCHOT# is routed between CPU and IMVP6
VR , Rtt has to be 68 ¡Ó5%.
If PROCHOT# is routed between CPU, IMVP6 VR
and GMCH, Rtt has to be 75 ¡Ó5%.
All manuals and user guides at all-guides.com
4
H_ADS# 4
H_BNR# 4
H_BPRI# 4
H_DEFER# 4
H_DRDY # 4
H_DBSY # 4
H_BR0# 4
H_INIT# 14
H_LOCK# 4
H_CPURST# 4
H_RS#0 4 4 H_DSTBN#0
Zo=55 Ohm
H_RS#1 4 4
H_RS#2 4 4
H_TRDY # 4
4
H_HIT# 4
H_HITM# 4
Voltage
translation
FROM IMVP6
Layout note:
4 H_DSTBN#1
4
PM_THRMTRIP# should connect to
4
PM_THRMTRIP# 5,14 ICH7 and GMCH without T-ing
PM_THRMTRIP# 5,14
CLK_CPU_BCLK 19
CLK_CPU_BCLK# 19
Layout Note:
0.5" max, Zo= 55 Ohms CPU_GTLREF
C229
1u/6.3V_X7R
9/13 4.0
+V_THRM
R583 *0_04
Q51
NDS352 R286 0_04
S D Z0223
Z0225
C444 0.01u_04
R284 C422
R296 100K_04 *1u/10V
100K_04
U26
Z0224
1
VDD
R297 330K_04 H_THERMDA 9/13 4.0 2
D+
C428
G
THERMAL_RST#
Q52 1000p_04 3
D-
2N7002W H_THERMDC 5
GND
Zo=60 Ohm ADM1032
9/13 4.0
Layout Note: Layout Note:
Route H_THERMDA and Near to Thermal
H_THERMDC on same layer. IC
10 mil trace on 10 mil spacing.
U28B
H_D#[63:0]
H_D#0 E22 AA23 H_D#32
D[0]# D[32]#
H_D#1 H_D#33
F24 AB24
D[1]# D[33]#
H_D#2 E26 V24 H_D#34
D[2]# D[34]#
H_D#3 H22 V26 H_D#35
D[3]# D[35]#
H_D#4 F23 W25 H_D#36
D[4]# D[36]#
H_D#5 H_D#37
G25 U23
D[5]# D[37]#
H_D#6 E25 U25 H_D#38
D[6]# D[38]#
H_D#7 E23 U22 H_D#39
D[7]# D[39]#
H_D#8 H_D#40
K24 AB25
D[8]# D[40]#
H_D#9 G24 W22 H_D#41
D[9]# D[41]#
H_D#10 J24 Y 23 H_D#42
D[10 D[42]#
H_D#11 H_D#43
J23 AA26
D[11]# D[43]#
H_D#12 H_D#44
H26 Y 26
D[12]# D[44]#
H_D#13 F26 Y 22 H_D#45
D[13]# D[45]#
H_D#14 K22 AC26 H_D#46
D[14]# D[46]#
H_D#15 H_D#47
H25 AA24
D[15]# D[47]#
H23 W24
DSTBN[0]# DSTBN[2]#
G22 Y 25
H_DSTBP#0
DSTBP[0]# DSTBP[2]#
J26 V23
H_DINV#0 DINV[0]# DINV[2]#
H_D#[63:0]
H_D#16 N22 AC22 H_D#48
D[16]# D[48]#
H_D#17 H_D#49
K25 AC23
D[17]# D[49]#
H_D#18 P26 AB22 H_D#50
D[18]# D[50]#
H_D#19 R23 AA21 H_D#51
D[19]# D[51]#
H_D#20 H_D#52
L25 AB21
D[20]# D[52]#
H_D#21 H_D#53
L22 AC25
D[21]# D[53]#
H_D#22 L23 AD20 H_D#54
D[22]# D[54]#
H_D#23 M23 AE22 H_D#55
D[23]# D[55]#
H_D#24 H_D#56
P25 AF23
D[24]# D[56]#
H_D#25 P22 AD24 H_D#57
D[25]# D[57]#
H_D#26 P23 AE21 H_D#58
D[26]# D[58]#
H_D#27 T24 AD21 H_D#59
D[27]# D[59]#
H_D#28 H_D#60
R24 AE25
D[28]# D[60]#
H_D#29 L26 AF25 H_D#61
D[29]# D[61]#
H_D#30 T25 AF22 H_D#62
D[30]# D[62]#
H_D#31 H_D#63
N24 AF26
D[31]# D[63]#
M24 AD23
DSTBN[1]# DSTBN[3]#
N25 AE24
H_DSTBP#1
DSTBP[1]# DSTBP[3]#
M26 AC20
H_DINV#1 DINV[1]# DINV[3]#
AD26 R26 COMP0
GTLREF COMP[0]
U26 COMP1
MISC
COMP[1]
COMP2
U1
COMP[2]
R304 *1K_04 Z0221 C26 V1 COMP3
TEST1 COMP[3]
R306 51.1_1%_04 Z0222 D25 E5
TEST2 DPRSTP#
13-51R11-28C B5
DPSLP#
package: 0402 D24
DPWR#
B22 D6
4 CPU_BSEL0
BSEL[0] PWRGOOD
B23 D7
4 CPU_BSEL1 BSEL[1] SLP#
C21 AE6
4 CPU_BSEL2
BSEL[2] PSI#
CPU
Zo=60 Ohm
Layout note:
COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms
R170 1K_1%_04
+1.05VS
COMP1, COMP3: 0.5" Max, Zo=55
Best estimate is 18 mils wide trace for outer
C212 C206 R174
layers and 14 mils wide trace if on internal
0.1u_X7R_04 0.01u_04 2K_1%_04
layers.
COMP0
COMP1
COMP2
COMP3
+H8VCC
R40 R39 R38
9/13 4.0 4.7K_04 4.7K_04 10K_04 D11 SCS751V
C A
Z0226
4 R584 * 0_04
THERM
6 Z0227 R585 0_04
ALERT
7
SMD_THERM 23
SDATA
8
SMC_THERM 23
SCLK
+1.05VS 3,4,7,8,9,14,17,31
+3VS 5,8,9,10,13,14,15,16,17,18,19,20,21,22,24,25,26,27
+H8VCC 19,23,27,30,32
Schematic Diagrams
H_D#[63:0] 4
H_DSTBN#2 4
H_DSTBP#2 4
Sheet 2 of 34
H_DINV#2 4
Zo=55 Ohm
H_D#[63:0] 4
Yonah 1/2
H_DSTBN#3 4
H_DSTBP#3 4
H_DINV#3 4
H_DPRSTP# 14,29
H_DPSLP# 14
H_DPWR# 4
H_PWRGD 14
H_CPUSLP# 4
PSI# 29
Ohms
R331 R327 R326 R325
54.9_1%_04 27.4_1%_04 54.9_1%_04 27.4_1%_04
PM_THRM# 16
THERM_TRIP# 23
Yonah 1/2 B - 3