Sun Microsystems SPARCserver 1000 System Installation Manual page 60

MXCC (Module XBus Cache Controller)
NVSIMM
Power-on Reset
Processor Bus
Processor
Replaceable Unit
Glossary-6
The MXCC ASIC is located on the processor module and controls flow of data
between the XBus and the module cache RAM and processor chip.
BW
The nonvolatile SIMM (NVSIMM) design incorporates a battery on the device
to prevent data loss in the event of power failure. Battery current is shared
among a group of NVSIMMs. This feature prevents memory failure should one
battery fail.
Reset signals produced by reset circuitry on the control board. At power-on,
reset is asserted for 200msec and is distributed to each system board to
initialize all ASICs. The reset PAL maintains system reset until Vtt is ready.
Found only on the SuperSPARC module. To compare bus types, see Bus.
See SuperSPARC Module.
Replaceable units are server subassemblies which can be replaced at the
customer site by trained, qualified service personnel.
SPARCserver 1000 System Installation Manual—June 1996
XDBus
BW
XBus
MXCC
R
A
M
Processor