Sun Microsystems SPARCserver 1000 System Installation Manual page 57

Board ID
BootBus
Bus
BW (Bus Watcher)
Cache
CARB (Central Arbiter)
Card
Slot identification codes are hardwired into the backplane. These codes
functionally configure the board for the slot address it occupies. System boards
can be installed in any slot without need for jumper (or other) configuration.
The BootBus is located on the system board. This bus connects the OpenBoot
EPROM set on system board to the SPARC module(s). See also Bus.
There are six basic types of busses in the SPARCserver 1000 system:
•
XDBus—the card cage backplane bus.
•
XBus—used for high bandwidth on system boards: between BW chips and
SuperSPARC modules, and between IOC and SBI chips.
•
SBus—services SBus cards on system boards.
•
Processor bus—found only on the SuperSPARC module.
•
BootBus—this system board bus connects the OpenBoot EPROM to the
SuperSPARC module.
•
JTAG—for factory use only.
The system board has two BWs (one for each processor). BWs convert XDBus
signals to XBus signals and pass them to the cache controller (MXCC) on the
processor module. Together, the BWs and MXCC control the flow of
information between the XDBus and the processors (and their respective cache
SRAMs).
The system design places a number of memory caches adjacent to various
busses for more efficient data transfer.
A system of central arbiters (one CARB on the control board) and a board
arbiter (one BARB on every system board) determine which processor on
which system board controls the system bus at any given time.
In this manual, the term card refers to a 3x5-inch SBus card. See also Board,
Module, and SBus Card. An exception is the disk card.
Glossary-3