Renesas Renasas Single-Chip Microcomputer SH7086 User Manual page 23

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Table2.3.2 lists an example of bus state controller settings for operation with the SH7086 Bus clock at 40MHz.
User Area
CS3 CS3 Space Bus Control Register(CS3BCR)
Initial value :H'36DB 0600
Recommended set value : H'1000 4400
- Specify idle cycles between write-read cycles and write-write cycles
IWW[2:0] = 001 ; 1 idle cycle inserted
- Specify memory type : TYPE[2:0] = 100 ;SDRAM
- Data bus size : BSZ[1:0] = B'10 ;16-bit size
CS3 Space Wait Control Register(CS3WCR)
Initial value : H'0000 0500
Recommended set value :H'0000 4891
- Number of Auto-Precharge Completion Wait Cycles
TRP[1:0] = 10 ;3 cycles
- Wait Cycles between ACTV Command and READ(A)/WRIT(A) Command
TRCD[1:0] = 10 ;3 cycles
- Area 3 CAS latency
A3CL[1:0] = 01 ;2 cycles
- WRIT(A) command→Number of Auto-Precharge/PRE Command cycles
TRWL[1:0] = 10 ;2 cycles
- REF Command/Self-Refresh Release →Number of ACTV/REF/MRS Command cycles.
TRC[1:0] = 01 ; 4 cycles
SDRAM Control Register(SDCR)
Initial value : H'0000 0000
Recommended set value : H'0000 0809
- Refresh control
RFSH = 1 ; Refresh enabled
- Refresh control
RMODE = 0 ; Auto refresh
- Bank active mode
BACTV = 0 ;Auto precharge mode
- Number of area3 row address bits
A3ROW[1:0] = 01 ;12 bits
- Number of area3 column address bits
A3COL[1:0] = 01 ;9 bits
Refresh Timer Control/Status Register(RTCSR)
Initial value : H'0000 0000
Recommended set value : H'A55A 0010
- Clock select
CKS[2:0] = 010 ;Bφ/16
- Refresh times
RRC[2:0] = 000 ; 1 time
Refresh Time Constant Register(RTCOR)
Initial value : H'0000 0000
Recommended set value : H'A55A 0027
*The following shows refresh request intervals in cases when clock select is set to Bφ/16.
1 cycle :400nsec(40MHz/16 = 2.5MHz)
Refresh request intervals for the SDRAM : every 15.625μsec
15.625μsec /400nsec = 39(0x27) cycles / refresh
Rev.1.0 Feb 06. 2007
REJ10J0916-0100
Table2.3.2 Example of Bus State Controller Settings at SDRAM
SDRAM Controller Settings
Functional Overview
2.3 Memory
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