Telos Zephyr User Manual page 210

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Pin 10 should be a constant DC voltage (with just a little ripple, maybe) at some
value between 1.5 and 6 Volts. A voltage at or near either ground or the 7.6 V
positive rail is indication of trouble.
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Pin 3 and 14 should have clock signals which are the same frequency and in- phase,
locked to each other.
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Pin 1 should be high.
Motherboard A-F: System Clock
System clock for the CPU and DSPs is generated by U19, a packaged oscillator,
operating at 50 MHz. U20 divides this to the various frequencies required. Sections of
U18 buffer the 50 MHz signal for driving the DSP chips.
Motherboard A-F: Xilinx
The two Xilinx chips, LCA1 and LCA2, are general purpose logic chips which
are loaded with software from the CPU in order to determine their operation
characteristics. Software is downloaded serially via XLNX- DIN (DataIN) and XLNX-
CCLK (bit CLK).
Once configured these chips make all the serial "pipeline" connections among
the DSPs and provide the switching and routing function to the selected digital interface
(V.35/ISDN/etc.), as described in Section 5.2. Both local and network reference clocks
are also generated within the Xilinx chips.
Since many of the DSP connections to the Xilinx chips are also software- configurable,
and since these connections depend on the specific operating mode, Xilinx pins may
sometimes be inputs but at other times outputs. This is different from bi- directional
pins because the hardware surrounding each Xilinx pin is set by software to be either
one way or the other on a per- configuration basis.
For troubleshooting purposes the most informative signal to look at is the
DONE/*PROG signal on pin 55 of each LCA (on the right- hand side of the chip as you
look at the part number, second pin from the bottom). This pin should be low during
the software download period (at powerup and during some mode changes), and will go
high as the chip becomes operational. If there is a problem with the download process
or the chip itself, this pin will remain low – and the chip will remain inactive.
Motherboard A-F: Microprocessor and Peripherals
The CPU and peripherals are a fairly straightforward, textbook Intel 801C88 processing
system. U1 is the CPU, U3,46 provided data/address bus de- muxing,
U2 is a buffer for the data bus. U17 buffers some of the other signals.
The UART, U9 and PIO, U10 are standard peripherals, using the 801C88's internal chip
selects for access. The UART is dual, and handles both the RS- 232 port and
the front panel RS- 485 connection via suitable drivers, U13/16 and U14, respectively.
Some of the UART's pins can be configured as parallel inputs or outputs and are used
for various I/Os. The 8255 is for additional parallel inputs
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Section 11 TECHNICAL INFORMATION