Commodore AMIGA Technical Manual page 33

AMIGA 1000 COMPONENT LEVEL REPAIR
BUS CONTROL, ADDRESS/DATA M U X , ADDRESS DRIVER
The bus control logic resides primarily in 4 PALs on the piggyback board. They provide the logic for
connecting the 6 8 0 0 0 buses to the display RAM buses when the 6 8 0 0 0 is attempting to access the
display RAM or the custom chips. To do this, the bus control logic must perform 3 major functions:
Synchronize the 6 8 0 0 0 to the current phase of C1
Arbitrate between the 6 8 0 0 0 and Agnus for the display buses
Turn on the muxes and bus drivers appropriate to the current cycle
Synchronizing the 6 8 0 0 0 to C1 is straightforward, since the 6 8 0 0 0 is clocked by 7M which is twice
the frequency and synchronous to C1. If the 6 8 0 0 0 starts a bus cycle in the wrong phase of C1,
the bus control logic merely delays /DTACK long enough so that the 6 8 0 0 0 will complete the bus
cycle in the desired phase relationship to C 1. This phase relationship is necessary because the custom
chips and the display RAM are clocked by C1.
Arbitration is very simple. Agnus tells the bus control prior to taking the display RAM buses by asserting
an input to the PALs called /DBR. Whenever Agnus has the display buses and the 6 8 0 0 0 wants them,
the 6 8 0 0 0 is held off by not giving it /DTACK. In this state the 6 8 0 0 0 has no affect on the display
buses until the bus controller enables the bus drivers and multiplexers, after Agnus has given up the
display buses.
DISPLAY RAM
The display RAM is an ordinary 256K byte read/write memory that resides on the RAM address and
RAM data buses. It is expandable to 5 1 2K bytes by the addition of the RAM expansion module. It
is implemented using standard dynamic RAMs, refreshed by Agnus.
The display RAM is really used for much more than just holding graphics data. It also stores code
and data for the 6 8 0 00.
1
-