Commodore AMIGA Technical Manual page 32

AMIGA 1000 COMPONENT LEVEL REPAIR
PROCESSOR RAM
This 256K byte RAM is intended to hold kernal and DOS routines. It has associated logic which allows
it to be write protected once it has been loaded. This allows it to function as ROM once the boot
load has been completed. Except during the boot sequence, " writes" to this RAM are prevented.
This RAM and its associated buffers and logic are resident on the piggyback board (daughter card},
which is attached to the main board.
PARALLEL I/O
The 2 multi-purpose 8 5 2 0 I/O chips provide the following:
I/O to and from the parallel port connector
Control lines to and from the joystick/mouse ports
A control line to the front panel LED
Internal control lines
Keyboard control lines, clock and data
Serial port control lines
Floppy disk interface control lines
Internal timers
These 2 chips reside on the 6 8 0 0 0 buses and are read and written by the 6 8 0 0 0 .
CLOCKS GENERATOR
The entire computer board is run synchronous to the 3 .5 7 9 5 4 5 MHz color clock. This is accomplished
by generating a number of submultiple frequencies from the master 2 8 .3 1 8 1 8 MHz crystal oscillator.
In order to reduce high frequency radiation, all clock generation is done in the small metal RF can
on the main logic board. The following are the primary clocks:
C1 3 .5 7 9 5 4 5 MHz color clock
C2 C1 shifted 45 degrees later
C3 C2 shifted 45 degrees later
C4 C3 shifted 45 degrees later
7M C1 XORed with C3 = 7 .1 5 9 0 9 MHz
/DAC 7M shifted 90 degrees later
THE 3 CUSTOM C HIPS
The 3 custom chips provide very fast manipulation of graphics and audio data in the display RAM.
All of the major functions in the chips are DMA driven; that is, streams of data are moved between
the custom chips and display RAM under DMA control. These streams of data are acted upon by the
custom chips. Agnus, custom chip #1, contains 25 dedicated purpose DMA counters.
The 3 chips have control registers which are usually loaded by the 6 8 0 0 0 . However, Agnus also has
the capability of loading control registers in the other 2 custom chips. When Agnus performs a bus
cycle, it outputs a code on the Register Address Bus telling the other 2 chips the nature of the bus
cycle. This is necessary because many of the bus cycles provide data to or from the other 2 chips,
thus they must cooperate appropriately.
In addition to manipulating data in the display RAM, the custom chips output streams of data to the
video output circuits, audio output circuits and move data to and from the floppy disks and serial port.
Note that the display RAM buses can be completely isolated from the 6 8 0 0 0 buses by the multiplexers
and drivers. Thus, Agnus can be performing a bus cycle on the display buses simultaneously with
the 6 8 0 0 0 performing a bus cycle on its buses. This parallelism increases throughput.
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