Details Of I/O Signals - Mitsubishi Electric Melsec Q Series User Manual

5 I/O signal to CPU module

5.2 Details of I/O signals

Detailed explanation about I/O signals of QE81WH is provided as follows:
5.2.1 Input signals
(1) Module ready (Xn0)
(a) When the power of CPU module is turned on or the CPU module reset is performed, it will
turn ON as soon as the measurement is ready.
(b)This signal (Xn0) is turned OFF when energy measuring module displays a hardware error,
and RUN LED is turned off.
(2) Periodic electric energy 1 data completion flag (Xn1)
(a) When Periodic electric energy 1 measurement flag (Yn1) is turned OFF and calculation
of the periodic electric energy 1 is stopped, then this signal (Xn1) turns ON. While
calculating the periodic electric energy 1, this signal (Xn1) turns OFF.
(b) In order to acquire the data under the condition where the periodic electric energy 1 is
checked after the accumulation of the periodic electric energy is stopped, obtain the data
while this signal (Xn1) is ON.
*For specific usage procedures, refer to section 4.2.2.
(3) Periodic electric energy 2 data completion flag (Xn2)
The usage procedure is the same as Periodic electric energy 1 data completion flag (Xn1).
Refer to (2).
(4) Periodic electric energy 1 reset completion flag (Xn3)
(a) When Periodic electric energy 1 reset request (Yn3) is turned ON, and the periodic electric
energy 1 that is stored in the buffer memory is reset, then this signal (Xn3) turns ON.
*For specific usage procedures, refer to section 4.2.2.
(5) Periodic electric energy 2 reset completion flag (Xn4)
The usage procedure is the same as Periodic electric energy 1 reset completion flag (Xn3).
Refer to (4).
(6) Data acquisition clock (Xn8)
(a) When the power is supplied to the CPU module and immediately after the initial
computation is performed, this signal (Xn8) is turned ON and count of the output period of
data acquisition clock is started. After that, this signal turns ON at the timing when the
measurement data is completely written into the buffer memory after the elapse of the
output period of data acquisition clock.
If the settings of the phase wire system, primary voltage, primary current, primary voltage
of VT, secondary voltage of VT, primary current of CT and output period of data
acquisition clock are changed, this signal turns ON immediately after the change of the
settings and count of the output period of data acquisition clock is started.
(b) This signal (Xn8) turns OFF 150 ms after it turns ON.
5 – 2
QE81WH