Quectel EG915U Series Hardware Design page 48

Te standard module
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MAIN_RTS
MAIN_RXD
MAIN_DCD
MAIN_TXD
MAIN_RI
MAIN_DTR
Table 15: Pin Definition of Debug UART Interface
Pin Name
Pin No.
DBG_RXD
22
DBG_TXD
23
Table 16: Auxiliary UART
Pin Name
Pin No.
AUX_TXD
27
AUX_RXD
28
The module provides 1.8 V UART interfaces. Use a level shifter if the application is equipped with a 3.3 V
UART interface. A level shifter TXS0108EPWR provided by Texas Instruments is recommended. The
following figure shows a reference design.
VDD_EXT
0.1 μF
MAIN_RI
MAIN_DCD
MAIN_CTS
MAIN_RTS
MAIN_DTR
MAIN_TXD
MAIN_RXD
EG915U_Series_Hardware_Design
37
DI
34
DI
38
DO
35
DO
39
DO
30
DI
I/O
Description
DI
Debug UART receive
DO
Debug UART transmit
I/O
Description
DO
Auxiliary UART transmit
DI
Auxiliary UART receive
VCCA
120K
OE
A1
A2
Translator
A3
A4
A5
A6
A7
51K
A8
DTE request to send signal to
DCE (connect to DTE's RTS)
Main UART receive
Main UART data carrier detect
Main UART transmit
Main UART ring indication
Main UART data terminal ready
Comment
1.8 V power domain.
If unused, keep it open.
Comment
1.8 V power domain.
If unused, keep it open.
VCCB
0.1 μF
GND
B1
B2
B3
CTS_MCU
B4
RTS_MCU
B5
DTR_MCU
B6
RXD_MCU
B7
TXD_MCU
51K
B8
LTE Standard Module Series
open.
VDD_MCU
RI_MCU
DCD_MCU
Connect the MCU CTS pin
Connect the MCU RTS pin
Connect the MCU RXD pin
Connect the MCU TXD pin
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