Ads8350Evm Analog Interface Input Connections; Jp1 And Jp2: Analog Interface Connections; Sma Analog Interface Connections - Texas Instruments ADS8350EVM-PDK User Manual

EVM Analog Interface
AIN_A
SMA J1
Header JP1.2
V
ref_A
AIN_B
SMA J2
Header JP2.2
V
ref_B
Figure 1. ADS8350EVM Analog Interface Input Connections
Table 1 summarizes the JP1 and JP2 analog interface connectors.
Terminal Number
JP1.2
JP2.2
Table 2 lists the SMA analog inputs.
Terminal Number
J1
J2
4
ADS8350EVM-PDK
OPA836
Inverting Configuration
AVDD
V
CM
+
OPA836 Buffer
OPA836
Inverting Configuration
AVDD
V
CM
+
OPA836 Buffer
Table 1. JP1 and JP2: Analog Interface Connections
Signal
Channel A inverted input. The signal is routed through an
AIN_A
OPA836 in the inverting configuration.
Channel B inverted input. The signal is routed through an
AIN_B
OPA836 in the inverting configuration.
Table 2. SMA Analog Interface Connections
Signal
Channel A inverted input. The signal is routed through an
AIN_A
OPA836 in the inverting configuration.
Channel B inverted input. The signal is routed through an
AIN_B
OPA836 in the inverting configuration.
Copyright © 2014, Texas Instruments Incorporated
AINP-A (Pin 15)
AINM-A (Pin 16)
JP7
AINP-B (Pin 6)
AINM-B (Pin 5)
JP8
Description
Description
SBAU218A – April 2014 – Revised October 2014
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ADS8350