Camera Block Diagram - GigE VA Series User Manual

5.3

Camera Block Diagram

CCD
Sensor
All controls and data processing of VA GigE cameras are carried out in one FPGA chip. The FPGA generally
consists of a 32 bit RICS Micro-Controller and Processing & Control Logic. The Micro-Controller receives
commands from the user through the Gigabit Ethernet interface and then processes them. The FPGA controls
the Timing Generators (TGs) and the Analog Front End (AFE) chips where the TGs generate CCD control
signals and AFE chips convert analog CCD output to digital values to be accepted by the Processing & Control
Logic. The Processing & Control Logic processes the image data received from AFE and then transmits data
through the Gigabit Ethernet interface. And also, the Processing & Control Logic controls the trigger input and
output signal which are sensitive to time. Furthermore, DDR2 for operating Micro-Controller and for used as
Gigabit Ethernet frame buffer, SDRAM for used as a frame buffer to process images, Gigabit Ethernet Controller
and Flash memory for saving system codes and defect coordinates are installed outside FPGA.
V Driver
ADC
(14bit)
H Driver
FLASH
Figure 5.1 Camera Block Diagram
12 of 94
FPGA
Image Processing
Control Logic
Micro Controller
EEPROM
VA GigE series
Optocoupler
Ext.trigger
Line Driver
Prog.output
DDR2
SDRAM
Ethernet
Network
Controller
RA14-131-003