Digital Interface; Parallel Interface; Serial Interface (Spi); I 2 C Bus And Eeprom - Texas Instruments ADS8555EVM-PDK User Manual

Digital Interface

3 Digital Interface
As noted in Section 1.1, the EVM interfaces with the PHI and communicates with the computer over the
USB. There are two devices on the EVM with which the PHI communicates: the ADS8555 ADC (over SPI or
parallel) and the EEPROM (over I
comes preprogrammed with the information required to configure and initialize the ADS8555 platform. When the
hardware is initialized, the EEPROM is no longer used.

3.1 Parallel Interface

The parallel interface signals are generated on the PHI controller and are connected through J2. Each of these
signals has a 47-Ω resistor between the device and the controller to slow down the signal edges in order to
minimize signal overshoot. The digital signals can be monitored on the J3, J4, and J5 test headers.

3.2 Serial Interface (SPI)

The ADS8555 ADC uses SPI serial communication in mode 1 (CPOL = 0 and CPHA= 1). Because the serial
clock (SCLK) frequency can be as fast as 36 MHz, the ADS8555EVM offers 47-Ω resistors between the
controller and device to aid with signal integrity. Typically, in high-speed SPI communication, fast signal edges
can cause overshoot; these 47-Ω resistors slow down the signal edges in order to minimize signal overshoot.
2
3.3 I C Bus and EEPROM
The circuit shown in Figure 3-1
required by the ADS8555 for operation. The switch (S1) is write protected and does not need to be changed for
EVM operation.
6 ADS8555EVM-PDK Evaluation Module
2
C). The electrically erasable programmable read-only memory (EEPROM)
is used with the EVM controller (PHI) for EVM identification. This circuit is not
EVM_ID_PWR
U3
1 8
A0 VCC
2 7
A1 WP
3 6
A2 SCL
4 5
VSS SDA
BR24G32FVT-3AGE2
GND
2
Figure 3-1. I C Bus and EEPROM
Copyright © 2021 Texas Instruments Incorporated
EVM_ID_PWR
C74
R101
S1
10.0k
1
100nF
GND
2
EVM_ID_SCL
3
EVM_ID_SDA
GND
R102 EVM_ID_WP
0
SLAU298A – NOVEMBER 2009 – REVISED MAY 2021
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