Schematics - Texas Instruments ADS8555EVM-PDK User Manual

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7.3 Schematics

Figure 7-2 shows a schematic for the amplifier drive section of the ADS8555EVM. The amplifier is by default a buffer and can be bypassed by using a
jumper.
J00
1
GN D
J01
1
GN D
J02
1
GN D
J03
1
GN D
SLAU298A – NOVEMBER 2009 – REVISED MAY 2021
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C02
DN P
JP0 0
100p F
TP9
R02 R03
A0
DN P
1.00k 0
HV DD
R04
GN D
C03
24.9
TP10
A0in 100n F
4 GN D
1
R01
3
U00
1.00k
OPA209 AIDBVR
C01
1000 pF C04
100n F
HV S S GN D
GN D
C12
DN P
100p F JP0 1
TP11
R12 R13
A1
DN P
1.00k
0
HV DD
GN D R14
C13
24.9
TP12
A1in 100n F
4 GN D
1
R11
3
1.00k U01
OPA209 AIDBVR
C11
C14
1000 pF
100n F
HV S S GN D
GN D
C22
DN P
JP0 2
100p F
TP17
R22 R23
B0
DN P
1.00k 0
HV DD
R24
GN D
C23
24.9
TP18
B0in 100n F
4 GN D
1
R21 3
1.00k U02
OPA209 AIDBVR
C21
C24
1000 pF
100n F
HV S S GN D
GN D
C32
DN P JP0 3
100p F
TP19
R32 R33
B1
DN P
1.00k
0
HV DD
R34
GN D C33
24.9
TP20
B1in 100n F
4 GN D
1
R31 3
1.00k U03
OPA209 AIDBVR
C31 C34
1000 pF
100n F
HV S S GN D
GN D
Figure 7-2. Amplifier Drive Schematic
Copyright © 2021 Texas Instruments Incorporated
CH_A0
C42
DN P
C05 100p F
220p F
R43
R42
DN P
1.00k
0
HV DD
GN D GN D C43
TP14
C0in 100n F
4
J04
1 R41 3
1.00k U04
OPA209 AIDBVR
C41
C44
1000 pF
100n F
HV S S
GN D
GN D
CH_A1
C52
DN P
C15 100p F
220p F
R53
R52
DN P
1.00k
0
HV DD
GN D GN D C53
TP16
C1in 100n F
4
J05
1 R51 3
1.00k U05
OPA209 AIDBVR
C51
C54
1000 pF
100n F
HV S S
GN D
GN D
CH_B0
C25
220p F
GN D
CH_B1
C35
220p F
GN D
Bill of Materials, Layout, and Schematics
JP0 4
TP13
C0
R44
CH_C 0
24.9
C45
220p F
GN D
1
GN D
GN D
JP0 5
TP15
C1
R54
CH_C 1
24.9
C55
GN D 220p F
1
GN D
GN D
ADS8555EVM-PDK Evaluation Module 23