EVM Analog Interface
2 EVM Analog Interface
The ADS8555EVM is an evaluation module built using a two-board modular EVM system. One board is a digital
controller (PHI), and the other board contains the ADC and associated analog circuitry. Both boards and the
associated cables form the ADS8555EVM-PDK.
2.1 ADC Supply, Input, Voltage Reference, and Digital Connections
Figure 2-1
shows the decoupling on AVDD, BVDD, HVDD, and HVSS and the voltage reference. The decoupling
capacitors match the recommendations in the
shortest possible connections to the decoupling capacitors and connects the ground end to the GND plane
using vias. The ADS8555 can use an external or internal voltage reference. This reference can be selected by
changing the position of JP06 to INT for internal or EXT for external.
signal and digital signal connections.
AVDD
C1
1µF
C2
1µF
C6
C3
1µF
1µF
C7
C4
1µF
1µF
GND
GND
U 2B
26
AV DD
AGND
34
AV DD
AGND
35
AV DD
AGND
40
AV DD
AGND
41
AV DD
AGND
46
AV DD
AGND
47
AV DD
AGND
50
AV DD
AGND
60
AV DD
AGND
AGND
AGND
BVDD
AGND
9
BV DD
BGND
31
HVDD
HVDD
HVSS
C28
1µF
ADS8555SPMR
C27
1µF
GND
GND
AVDD
U6A
2
VIN
3
TEMP
C39
REF5025AIDGKR
100nF
GND
4
ADS8555EVM-PDK Evaluation Module
ADS8555 data
CH_A0
33
CONVST_A
R97
23
49.9
C71
54
25
GND
10uF
32
CH_A1
36
37
38
43
CH_B0
39
44
49
CONVST_B
R98
22
52
49.9
53
C72
56
55
GND
10uF
57
CH_B1
42
59
8
GND
CH_C0
45
30
GND
HVSS
CONVST_C
R99
49.9
C73
58
C5
GND
10uF
1µF
CH_C1
48
GND
TP8
VREF
JP06
EXT
INT
R47
0
6
VOUT
5
TRIM/NR
4
GND
C37
1µF
R48
0.22
C38
GND
10uF
GND
Figure 2-1. ADC Signal and Supply Connection
Copyright © 2021 Texas Instruments Incorporated
sheet. The layout (see
Figure 2-1
U 2A
18
CH_A0
BU SY/INT
27
RA NGE/XC LK
62
CONVS T_A
HW/SW
63
REFEN/WR
24
REFC_A
STB Y
28
RES ET
CH_A1
19
CS /FS
20
RD
29
CH_B0
WOR D/B YTE
61
PAR/S ER
CONVS T_B
17
DB0/SEL _A
16
REFC_B
DB1/SEL _B
15
DB2/SEL _C
14
CH_B1
DB3/DCIN_C
13
DB4/DCIN_B
12
DB5/DCIN_A
11
CH_C 0
DB6/SC LK
10
DB7/HBEN/DCEN
21
7
CONVS T_C
DB8/SDO_A
6
DB9/SDO_B
5
REFC_C
DB10/SDO_C
4
DB11
3
CH_C 1
DB12
2
DB13/SDI
1
DB14/REFBU FEN
51
64
REFIO
DB15
ADS8555SPMR
C40
470nF
25V
GND
SLAU298A – NOVEMBER 2009 – REVISED MAY 2021
www.ti.com
Figure
7-1) uses the
also shows the analog input
R71
BUSY/INT
R72
49.9
RANGE/XCLK
49.9
R73
HW/SW
R74
49.9
REFEN/WR
49.9
R75
ST BY
R76
49.9
RESET
49.9
R77
CS/FS
R46
49.9
~RD_RETURN
R78
49.9
~RD
49.9
R79
WORD/BYTE
R80
49.9
PAR/SER
49.9
R81
DB0/SEL_A
R82
49.9
DB1/SEL_B
49.9
R83
DB2/SEL_C
R84
49.9
DB3/DCIN_C
49.9
R85
DB4/DCIN_B
R86
49.9
DB5/DCIN_A
49.9
R87
DB6/SCLK
R35
49.9
SCLK_RET URN
49.9
R88
DB7/HBEN/DCEN
49.9
R89
DB8/SDO_A
R90
49.9
DB9/SDO_B
49.9
R91
DB10/SDO_C
R92
49.9
DB11
49.9
R93
DB12
R94
49.9
DB13/SDI
49.9
R95
DB14/REFBUFEN
R96
49.9
DB15
49.9
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