Specifications - Stanford Research Systems SR830 Manual

SPECIFICATIONS

SIGNAL CHANNEL
Voltage Inputs
Current Input
Full Scale Sensitivity
Input Impedance
Gain Accuracy
Input Noise
Signal Filters
CMRR
Dynamic Reserve
Harmonic Distortion
REFERENCE CHANNEL
Frequency Range
Reference Input
Phase Resolution
Absolute Phase Error
Relative Phase Error
Orthogonality
Phase Noise
Phase Drift
Harmonic Detect
Acquisition Time
DEMODULATOR
Zero Stability
Time Constants
Harmonic Rejection
INTERNAL OSCILLATOR
Frequency
Frequency Accuracy
Frequency Resolution
Distortion
Output Impedance
Amplitude
Amplitude Accuracy
Amplitude Stability
Outputs
SR830 DSP LOCK-IN AMPLIFIER
Single-ended (A) or differential (A-B).
6 8
10 or 10 Volts/Amp.
2 nV to 1 V in a 1-2-5-10 sequence (expand off).
Voltage: 10 MΩ+25 pF, AC or DC coupled.
Current: 1 kΩ to virtual ground.
±1% from 20°C to 30°C (notch filters off), ±0.2 % Typical.
6 nV/√Hz at 1 kHz (typical).
60 (50) Hz and 120(100) Hz notch filters (Q=4).
100 dB to10 kHz (DC Coupled), decreasing by 6db/octave above 10 kHz
Greater than 100 dB (with no signal filters).
-80 dB.
1 mHz to 102 kHz
TTL (rising or falling edge) or Sine.
Sine input is1 MΩ, AC coupled (>1 Hz). 400 mV pk-pk minimum signal.
0.01°
<1°
<0.01°
90° ± 0.001°
External synthesized reference: 0.005° rms at 1 kHz, 100 ms, 12 dB/oct.
Internal reference: crystal synthesized, <0.0001° rms at 1 kHz.
<0.01°/°C below 10 kHz
<0.1°/°C to 100 kHz
Detect at Nxf where N<19999 and Nxf<102 kHz.
(2 cycles + 5 ms) or 40 ms, whichever is greater.
Digital displays have no zero drift on all dynamic reserves.
Analog outputs: <5 ppm/°C for all dynamic reserves.
10 µs to 30 s (reference > 200 Hz). 6, 12, 18, 24 dB/oct rolloff.
up to 30000 s (reference < 200 Hz). 6, 12, 18, 24 dB/oct rolloff.
Synchronous filtering available below 200 Hz.
-80 dB
1 mHz to 102 kHz.
25 ppm + 30 µHz
4 1/2 digits or 0.1 mHz, whichever is greater.
f<10 kHz, below -80 dBc. f>10 kHz, below -70 dBc.1 Vrms amplitude.
50 Ω
4 mVrms to 5 Vrms (into a high impedance load) with 2 mV resolution.
(2 mVrms to 2.5 Vrms into 50Ω load).
1%
50 ppm/°C
Sine output on front panel. TTL sync output on rear panel.
When using an external reference, both outputs are phase locked to the
external reference.
1-5