Stanford Research Systems SR830 Manual page 146

CPU and POWER SUPPLY BOARD
The CPU board contains the microprocessor
system. All display, front panel, disk, and comput-
er interfaces are on this board.
MICROPROCESSOR SYSTEM
The microprocessor, U101, is an 80C186 micro-
controller which integrates a fast 16 bit processor,
counter-timers, interrupt controller, DMA controller,
and I/O decoding into a single component.
The 80C186 uses a 24.00 MHz crystal, X101, as
its oscillator. The instruction clock cycle is 2 oscil-
lator cycles or 12.0 MHz. The data and lower 16
bits of address are multiplexed on AD0-AD15.
U201, U202, U203 latch the address A0-A19 at
the beginning of each memory or I/O cycle. U204
and U205 are bidirectional data bus drivers which
are active during the data read/write portion of
each memory or I/O cycle.
The 80C186 can address 1 Mbyte of memory and
64k of I/O space. The memory is mapped into 2
256kbyte blocks. Each block has 2 sockets, one
for the low byte and one for the high byte of data.
U303 and U304 are 128kbyte EPROMS holding
the program boot firmware. This memory is
mapped at C0000H to FFFFFH (256k).
U401 and U402 are 128kbyte CMOS static RAMs
mapped at 00000H to 3FFFFH (256k). U401 and
U402 are backed up by the battery. Q401 provides
power down RAM protection. This memory is
system memory.
3 of the 7 80C186's peripheral chip select strobes
are used by peripherals on the CPU board. -PCS0
is decoded into 16 I/O strobes which access the
displays, keypad and knob, etc. -PCS1 decodes
the the GPIB controller. -PCS2 selects the UART.
FRONT PANEL INTERFACE
U614 and U615 buffer the front panel connector
cable. The Display Board holds the front panel
logic.
Circuit Description
SPIN KNOB
The knob is an optical encoder buffered by U612.
Each transition of its outputs is clocked into U610
or U611 and generates an interrupt at the output
of U602A. The processor keeps track of the knob's
position continuously.
SPEAKER
The speaker is driven by a timer on the 80C186.
The timer outputs a square wave which is enabled
by U602B and drives the speaker through Q705.
GPIB INTERFACE
The GPIB (IEEE-488) interface is provided by
U902, a TMS9914A controller. U903 and U904
buffer data I/O to the GPIB connector. U902 is pro-
grammed to provide an interrupt to the processor
whenever there is bus activity addressed to the
unit.
RS232 INTERFACE
The SCN2641 UART, U905, provides all of the
UART functions as well as baud rate generation.
Standard baud rates up to 19.2k can be generated
from the 3.6864 MHz clock. U906 buffers the out-
going data and control signals. Incoming signals
are received by U705A and U705B. If the host
computer asserts DTR, RS232 data output from
the unit will cease.
The RS232 port is a DCE and may be connected
to a PC using a standard serial cable (not a "null
modem" cable).
EXPANSION CONNECTOR
All control of the data acquisition hardware is
through the signals on the 30 pin expansion
connector.
7-3