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Arbor Technology EmETXe-i250C User Manual

Com express type 6 cpu module
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EmETXe-i250C
COM Express Type 6 CPU Module
User's Manual
Version 1.1
2016.09

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Summary of Contents for Arbor Technology EmETXe-i250C

  • Page 1 EmETXe-i250C COM Express Type 6 CPU Module User’s Manual Version 1.1 2016.09...
  • Page 2 This page is intentionally left blank.

  • Page 3: Table Of Contents

    Index Contents Chapter 1 - Introduction ............1 1.1 Copyright Notice ................2 1.2 Declaration of Conformity ............2 1.3 About This User’s Manual ............4 1.4 Warning ..................4 1.5 Replacing the Lithium Battery.............4 1.6 Technical Support ................4 1.7 Warranty ..................5 1.8 Packing List ..................6 1.9 Ordering Information ..............6 1.10 Specifications ................7 1.11 Board Dimensions ..............8...
  • Page 4 Index 3.3 Chipset ..................30 3.3.1 Host Bridge Parameters ........31 3.3.2 SB Configuration ..........35 3.4 Boot Settings ................40 3.5 Security ..................41 3.6 Save & Exit ..................43 3.7 AMI BIOS Checkpoints ...............44 3.7.1 Checkpoint Ranges ..........44 3.7.2 Standard Checkpoints .........45 Appendix ....................53 Appendix A: I/O Port Address Map ..........54 Appendix B: Interrupt Request Lines (IRQ) ........57 Appendix C: BIOS Memory Map ............58...

  • Page 5: Chapter 1 Introduction

    Introduction Chapter 1 Introduction Chapter 1 - Introduction - 1 -...

  • Page 6: Copyright Notice

    Introduction 1.1 Copyright Notice All Rights Reserved. The information in this document is subject to change without prior notice in order to improve the reliability, design and function. It does not represent a commitment on the part of the manufacturer. Under no circumstances will the manufacturer be liable for any direct, indirect, special, incidental, or consequential damages arising from the use or inability to use the product or documentation, even if advised of the possibility of such...
  • Page 7 RoHS ARBOR Technology Corp. certifies that all components in its products are in compliance and conform to the European Union’s Restriction of Use of Haz- ardous Substances in Electrical and Electronic Equipment (RoHS) Directive 2002/95/EC.

  • Page 8: About This User's Manual

    Introduction 1.3 About This User’s Manual This user’s manual provides general information and installation instructions about the product. This User’s Manual is intended for experienced users and integrators with hardware knowledge of personal computers. If you are not sure about any description in this booklet. please consult your vendor before further handling.

  • Page 9: Warranty

    Introduction 1.7 Warranty This product is warranted to be in good working order for a period of two years from the date of purchase. Should this product fail to be in good working order at any time during this period, we will, at our option, replace or repair it at no additional charge except as set forth in the following terms.

  • Page 10: Packing List

    1 x Quick Installation Guide If any of the above items is damaged or missing, contact your vendor immediately. 1.9 Ordering Information Intel® Atom™ D2550 1.86GHz COM EmETXe-i250C-D25 Express CPU module HS-250C-F2 Heat Spreader (95 x 95 x 11mm) HS-250C-W1 Heatsink wave type (95 x 95 x 23.2mm)

  • Page 11: Specifications

    Introduction 1.10 Specifications COM Express Type 6 CPU Module Form Factor Soldered onboard Intel ® Atom™ D2550 1.86GHz processor Intel ® PCH NM10 Chipset 1 x DDR3 SO-DIMM socket, supporting up to 4GB System Memory SDRAM Integrated Intel ® GMA 3650 (Gfx frequency Graphics 640MHz) ●...

  • Page 12: Board Dimensions

    Introduction 1.11 Board Dimensions 95.00 45.85 Ø2.70 NM10 SB Cedar View D 76.00 4.00 45.35 Unit: mm - 8 -...

  • Page 13: Chapter 2 Installation

    Installation Chapter 2 Installation Chapter 2 - Installation - 9 -...

  • Page 14: What Is "Com Express

    Installation 2.1 What is “COM Express”? With more and more demands on small and embedded industrial boards, a multi-functioned COM (Computer-on-Module) is the great one of the solutions. COM Express, board-to-board connectors consist of two rows of 220 pins each. Row AB, which is required, provides pins for PCI Express, SATA, LVDS, LCD channel, LPC bus, system and power management, VGA, LAN, and power and ground interfaces.
  • Page 15 Module Type 1 and 10 support single connector with two rows of pins (220 pins). Module Type 2, 3, 4, 5 and 6 support two connectors with four rows of pins (440 pins). EmETXe-i250C is a Type 6 module. Connector placement and most mounting holes have transparency between Form Factors.

  • Page 16: Block Diagram

    Installation 2.2 Block Diagram Single Channel DDR3 1 x SO-DIMM socket 800/ 1067MHz DDI0 (TMDS/ DVI/DP) Intel® Atom DDI1 (TMDS/ DVI/DP/eDP) D2550 at 1.86GHz Analog R.G.B. 24-bit Single Channel LVDS DMIx4 for Cedarview-D HD Audio Link Intel 82583V GbE LAN1 PCIex1 GbE controller 8 x USB ports...

  • Page 17: Connectors

    Installation 2.3 Connectors Top side SO-DIMM socket NM10 SB Cedar View D Bottom side COM Express AB Connector COM Express CD Connector COM Express CD Connector COM Express AB Connector - 13 -...

  • Page 18: Com Express Ab Connector (Bottom Side)

    Installation 2.4 COM Express AB Connector (bottom side) PCIE_RX4- PCIE_TX4- GBE0_ACT# GBE0_MDI3- GBE0_MDI3+ LPC_FRAME# PCIE_RX3+ PCIE_TX3+ LPC_AD0 GBE0_LINK100# PCIE_RX3- PCIE_TX3- LPC_AD1 GBE0_LINK1000# GBE0_MDI2- LPC_AD2 PCIE_RX2+ PCIE_TX2+ LPC_AD3 GBE0_MDI2+ PCIE_TX2- PCIE_RX2- LPC_DRQ0# GBE0_LINK# GPO3 GPI1 GBE0_MDI1- LPC_DRQ1# PCIE_RX1+ PCIE_TX1+ LPC_CLK GBE0_MDI1+ PCIE_TX1- PCIE_RX1- WAKE0#...

  • Page 19: Com Express Cd Connector (Bottom Side)

    Installation 2.5 COM Express CD Connector (bottom side) GND (FIXED) GND (FIXED) TYPE2# TYPE1# GND (FIXED) GND (FIXED) RSVD RSVD RSVD RSVD GND (FIXED) GND (FIXED) RSVD RSVD GND (FIXED) DDI1_CTRLCLK_AUX+ GND (FIXED) DDI1_CTRLCLK_AUX- RSVD RSVD RSVD RSVD GND(FIXED) GND(FIXED) RSVD RSVD RSVD...

  • Page 20: The Installation Paths Of Cd Driver

    Installation 2.6 The Installation Paths of CD Driver Windows 7 Driver Path Chipset \EmETXe-i250x\CHIPSET\WIN7 \EmETXe-i250x\ETHERNET \EmETXe-i250x\GRAPHICS Audio \EmETXe-i250x\AUDIO - 16 -...

  • Page 21: Chapter 3 - Bios

    BIOS Chapter 3 BIOS Chapter 3 - BIOS - 17 -...

  • Page 22: Bios Main Setup

    BIOS 3.1 BIOS Main Setup The AMI BIOS provides a setup utility program for specifying the system configurations and settings which are stored in the BIOS ROM of the system. When you turn on the computer, the AMI BIOS is immediately activated. After you have entered the setup utility, use the left/right arrow keys to highlight a particular configuration screen from the top menu bar or use the down arrow key to access and configure the information below.

  • Page 23: Advanced Settings

    BIOS System Date Set the system date. Note that the ‘Day’ automatically changes when you set the date. The date format is: Day : Sun to Sat Month : 1 to 12 Date : 1 to 31 Year : 1999 to 2099 System Time Set the system time.

  • Page 24: Pci Subsystem Settings

    BIOS 3.2.1 PCI Subsystem Settings PCI ROM Priority In case of multiple Option ROMs (Legacy and EFI Compatible), specifies what PCI Option ROM to launch. PCI Latency Timer Value to be programmed into PCI Latency Timer Register. VGA Palette Snnop Enables or Disabled VGA Palette Registers Snooping.

  • Page 25: Acpi Settings

    BIOS 3.2.2 ACPI Settings Enable ACPI Auto Configuration Enables or disables BIOS ACPI Auto Configuration. Enable Hibernation Enable or disable System ability to Hibernation (OS/S4 Sleep State). This option may be not effective with some OS. ACPI Sleep State Select the highest ACPI sleep state the system will enter when the SUSPEND button is pressed.

  • Page 26: Cpu Configuration

    BIOS 3.2.3 CPU Configuration The CPU Configuration setup screen varies depending on the installed processor. Hyper-threading This item is used to enable or disable the processor’s Hyper-threading feature. Enabled for Windows XP and Linux (OS optimized for Hyper-threading Technology) and disabled for other OS (OS not optimized for Hyper-threading Technology).

  • Page 27: Ide Configuration

    BIOS 3.2.4 IDE Configuration It allows you to select the operation mode for SATA controller. SATA Controller(s) Enable or disable SATA devices. SATA Mode Selection The choice: Disable; IDE (Default), AHCI (not available in EmETXe-i65M2), RAID IDE: Set the Serial ATA drives as Parallel ATA storage devices. AHCI: Allow the Serial ATA devices to use AHCI (Advanced Host Controller Interface).

  • Page 28: Usb Configuration

    BIOS 3.2.5 USB Configuration Legacy USB Support Enable support for legacy USB. AUTO option disables legacy support if no USB devices are connected. The choice: Enabled (Default); Auto; Disabled EHCI Hand-off Allow you to enable support for operating systems without an EHCI hand-off feature.
  • Page 29 BIOS Device power-up delay Maximum time the device will take before it properly reports itself to the host controller. ‘Auto’ uses default value: for a Root port it is 100ms, for a Hub port the delay is taken from hub descriptor. The choice: Auto (Default); Manual - 25 -...

  • Page 30: Super Io Configuration

    BIOS 3.2.6 Super IO Configuration You can use this item to set up or change the Super IO configuration for parallel ports and serial ports. Power On After Power Failure Specify what state to go to when power is re-applied after a power failure. Power On by modem Function Enables or Disables the Power On by modem fuction.
  • Page 31 BIOS Serial Port 1~2 Configuration Serial Port Use the Serial port option to enable or disable the serial port. The choice: Enabled, Disabled Change Settings Use the Change Settings option to change the serial port’s IO port address and interrupt address. The choice: Auto IO=3F8h;...
  • Page 32 BIOS Parallel Port Configuration Parallel Port Configuration This item allows you to enable/disable Parallel Port (LPT/LPTE). Change Settings Use the Change Settings option to change the parallel port’s IO port address and interrupt address. The choice: Auto IO=378h; IRQ=5, IO=378h; IRO=5,6,7,10,11,12, IO=378h;...

  • Page 33: F71869 H/W Monitor

    BIOS 3.2.7 F71869 H/W Monitor PC Health Status The hardware monitor menu shows the operating temperature and system voltages of CPU module. - 29 -...

  • Page 34: Chipset

    BIOS 3.3 Chipset This section allows you to configure and improve your system; also, set up some system features according to your preference. - 30 -...

  • Page 35: Host Bridge Parameters

    BIOS 3.3.1 Host Bridge Parameters Memory Frequency and Timing - 31 -...
  • Page 36 BIOS MRC Fast Boot Enable or disable MRC fast boot. Dyn SR Enable or disable Dyn SR. - 32 -...
  • Page 37 BIOS Intel IGD Configuration Auto Disable IGD Auto disable IGD upon external GFX detected. IFGX - Boot Type Select the Video Device which will be activated during POST. This has no ef- fect if external graphics present. LCD Panel Type Select LCD panel used by Internal Graphics Device by selecting the appropri- ate setup item: VBIOS Default, 640x480 LVDS ~ 2048x1536 LVDS.
  • Page 38 BIOS ISD Clock Source ISD clock selection. Fixed Graphics Memory Size Configure fixed Graphics memory size. ALS Support The choice: Enabled, Disabled. Backlight Control Support Backlight control configuration. The choice: VBIOS Default, Disabled and Level 1/2/3/4/5. - 34 -...

  • Page 39: Sb Configuration

    BIOS 3.3.2 SB Configuration DMI Link ASPM Control The control of Active State Power Management on both NB side and SB side of the DMI Link. PCI-Exp. High Priority port Enables or Disables PCI-Exp. High Priority port. PCIE Card0/1 Enables or Disables PCIE Card0/1. High Precision TImer Enables or Disables High Precision Timer.
  • Page 40 BIOS Select USB Mode Select USB mode to control USB port. UHCI1~4 Control the USB UHCI (USB 1.1) functions. Disable from highest to lowest controller. USB 2.0 (EHCI) Support Enable or Disable USB 2.0 (EHCI). LAN controller Enable or Disable OnChip NIC Controller. SMBus controller Enable or Disable SMBus controller.
  • Page 41 BIOS TPT Deviced Enable/ Disable Intel(R) IO Controller Hub (TPT) devices. Azalia Controller Control detection of the Azalia device. Disabled = Azalia will be unconditionally disabled. AH Audio = Azalia will be enabled if present, disabled otherwise. Azalia PME Enable Enable or Disable Power Management capability of Audio Controller.
  • Page 42 BIOS PCI Express Root Port 0~5 PCI Express Root Port 0~5 Control the PCI Express Root Port. ASPM Support Set the ASPM Level to Disabled, L0s, L1, L0sL1, Auto Force L0 - Force all links to L0 State AUTO - BIOS auto configuration DISABLE - Disable ASPM - 38 -...
  • Page 43 BIOS Enable or disable PCI Express Unsupported Request Reporting. Enable or disable PCI Express Device Fatal Error Reporting. NFER Enable or disable PCI Express Device Non-Fatal Error Reporting. Enable or disable PCI Express Device Correctable Error Reporting. Enable or disable PCI Express Completion Timer TO. SEFE Enable or disable Root PCI Express System Error on Fatal Error.

  • Page 44: Boot Settings

    BIOS 3.4 Boot Settings The Boot menu items allow you to change the system boot options. Boot Configuration Bootup NumLock State This setting determines whether the Num Lock key should be activated at boot up. Quiet Boot This allows you to select the screen display when the system boots. Fast Boot Enables or disables boot with initialization of a minimal set of devices requered to launch active boot optoin.

  • Page 45: Security

    BIOS 3.5 Security Administrator Password Use the Administrator Password to set or change a administrator password. ENTER PASSWORD Type the password, up to eight characters in length, and press <Enter>. The password typed now will clear any previously entered password from CMOS memory.
  • Page 46 BIOS changing any part of your system configuration. Additionally, when a password is enabled, you can also require the BIOS to request a password every time your system is rebooted. This would prevent unauthorized use of your computer. You can determine when the password is required within the BIOS Features Setup Menu and its Security option.

  • Page 47: Save & Exit

    BIOS 3.6 Save & Exit Save Changes and Reset Pressing <Enter> on this item and it asks for confirmation: Save configuration changes and exit setup? Pressing <OK> stores the selection made in the menus in CMOS - a special section of memory that stays on after you turn your system off. The next time you boot your computer, the BIOS configures your system according to the Setup selections stored in CMOS.

  • Page 48: Ami Bios Checkpoints

    BIOS 3.7 AMI BIOS Checkpoints 3.7.1 Checkpoint Ranges Status Code Range Description 0x01 – 0x0B SEC execution 0x0C – 0x0F SEC errors PEI execution up to and including memory 0x10 – 0x2F detection 0x30 – 0x4F PEI execution after memory detection 0x50 –...

  • Page 49: Standard Checkpoints

    BIOS 3.7.2 Standard Checkpoints SEC Phase Status Code Description 0x00 Not used Progress Codes 0x01 Power on. Reset type detection (soft/hard). 0x02 AP initialization before microcode loading 0x03 North Bridge initialization before microcode loading 0x04 South Bridge initialization before microcode loading 0x05 OEM initialization before microcode loading 0x06...
  • Page 50 BIOS PEI Phase Status Code Description Progress Codes 0x10 PEI Core is started 0x11 Pre-memory CPU initialization is started 0x12 Pre-memory CPU initialization (CPU module specific) 0x13 Pre-memory CPU initialization (CPU module specific) 0x14 Pre-memory CPU initialization (CPU module specific) 0x15 Pre-memory North Bridge initialization is started Pre-Memory North Bridge initialization (North Bridge...
  • Page 51 BIOS 0x32 CPU post-memory initialization is started 0x33 CPU post-memory initialization. Cache initialization CPU post-memory initialization. Application Processor(s) 0x34 (AP) initialization CPU post-memory initialization. Boot Strap Processor 0x35 (BSP) selection CPU post-memory initialization. System Management 0x36 Mode (SMM) initialization 0x37 Post-Memory North Bridge initialization is started Post-Memory North Bridge initialization (North Bridge 0x38...
  • Page 52 BIOS 0x55 Memory not installed 0x56 Invalid CPU type or Speed 0x57 CPU mismatch 0x58 CPU self test failed or possible CPU cache error CPU micro-code is not found or micro-code update is 0x59 failed 0x5A Internal CPU error 0x5B reset PPI is not available 0x5C-0x5F Reserved for future AMI error codes...
  • Page 53 BIOS 0xF9 Recovery capsule is not found 0xFA Invalid recovery capsule 0xFB – 0xFF Reserved for future AMI error codes DXE Phase Status Code Description 0x60 DXE Core is started 0x61 NVRAM initialization 0x62 Installation of the South Bridge Runtime Services 0x63 CPU DXE initialization is started 0x64...
  • Page 54 BIOS South Bridge DXE Initialization (South Bridge module 0x74 specific) South Bridge DXE Initialization (South Bridge module 0x75 specific) South Bridge DXE Initialization (South Bridge module 0x76 specific) South Bridge DXE Initialization (South Bridge module 0x77 specific) 0x78 ACPI module initialization 0x79 CSM initialization 0x7A –...
  • Page 55 BIOS 0xA4 SCSI initialization is started 0xA5 SCSI Reset 0xA6 SCSI Detect 0xA7 SCSI Enable 0xA8 Setup Verifying Password 0xA9 Start of Setup 0xAA Reserved for ASL (see ASL Status Codes section below) 0xAB Setup Input Wait 0xAC Reserved for ASL (see ASL Status Codes section below) 0xAD Ready To Boot event 0xAE...
  • Page 56 BIOS 0xD7 No Console Input Devices are found 0xD8 Invalid password 0xD9 Error loading Boot Option (LoadImage returned error) 0xDA Boot Option is failed (StartImage returned error) 0xDB Flash update is failed 0xDC Reset protocol is not available ACPI/ASL Checkpoints Status Code Description 0x01...

  • Page 57: Appendix

    Appendix Appendix Appendix - 53 -...

  • Page 58: Appendix A: I/O Port Address Map

    Appendix Appendix A: I/O Port Address Map Each peripheral device in the system is assigned a set of I/O port addresses which also becomes the identity of the device. The following table lists the I/O port addresses used. Address Device Description 0x00000000-0x00000CF7 PCI bus 0x00000000-0x00000CF7...
  • Page 59 Appendix 0x000000BC-0x000000BD Programmable interrupt controller 0x000004D0-0x000004D1 Programmable interrupt controller 0x000004D0-0x000004D1 Motherboard resources 0x0000002E-0x0000002F Motherboard resources 0x0000004E-0x0000004F Motherboard resources 0x00000061-0x00000061 Motherboard resources 0x00000063-0x00000063 Motherboard resources 0x00000065-0x00000065 Motherboard resources 0x00000067-0x00000067 Motherboard resources 0x00000070-0x00000070 Motherboard resources 0x00000070-0x00000070 System CMOS/real time clock 0x00000080-0x00000080 Motherboard resources 0x00000080-0x00000080 Motherboard resources 0x00000092-0x00000092...
  • Page 60 Appendix 0x00000064-0x00000064 Standard 101/102-Key or Microsoft Natural PS/2 Keyboard 0x000003F8-0x000003FF Communications Port (COM1) 0x000002F8-0x000002FF Communications Port (COM2) 0x00000378-0x0000037F Printer Port (LPT1) 0x00000010-0x0000001F Motherboard resources 0x00000022-0x0000003F Motherboard resources 0x00000044-0x0000005F Motherboard resources 0x00000072-0x0000007F Motherboard resources 0x00000084-0x00000086 Motherboard resources 0x00000088-0x00000088 Motherboard resources 0x0000008C-0x0000008E Motherboard resources 0x00000090-0x0000009F Motherboard resources...

  • Page 61: Appendix B: Interrupt Request Lines (Irq)

    Appendix 0x000001CE-0x000001CF VgaSave 0x000002E8-0x000002EF VgaSave Appendix B: Interrupt Request Lines (IRQ) Peripheral devices use interrupt request lines to notify CPU for the service required. The following table shows the IRQ used by the devices on board. Level Function IRQ 9 Microsoft ACPI-Compliant System IRQ 16 PCI standard PCI-to-PCI bridge...

  • Page 62: Appendix C: Bios Memory Map

    Appendix Appendix C: BIOS Memory Map Address Device Description 0xA0000-0xBFFFF PCI bus 0xA0000-0xBFFFF VgaSave 0xD0000-0xD3FFF PCI bus 0xD4000-0xD7FFF PCI bus 0xD8000-0xDBFFF PCI bus 0xDC000-0xDFFFF PCI bus 0xE0000-0xE3FFF PCI bus 0xE4000-0xE7FFF PCI bus 0x7DA00000-0xFEAFFFFF PCI bus 0x7DA00000-0xFEAFFFFF Motherboard resources 0xF7800000-0xF7BFFFFF Video Controller (VGA Compatible) 0xE0000000-0xEFFFFFFF Video Controller (VGA Compatible) 0xF7C2B000-0xF7C2B00F...
  • Page 63 Appendix 0xFED19000-0xFED19FFF Motherboard resources 0xF8000000-0xFBFFFFFF Motherboard resources 0xFED20000-0xFED3FFFF Motherboard resources 0xFED90000-0xFED93FFF Motherboard resources 0xFED45000-0xFED8FFFF Motherboard resources 0xFEE00000-0xFEEFFFFF Motherboard resources 0x20000000-0x201FFFFF System board 0x40000000-0x401FFFFF System board - 59 -...

  • Page 64: Appendix D: Digital I/O Setting

    Appendix Appendix D: Digital I/O Setting Below are the source codes written in C, please take them for Digital I/O application examples. The default I/O address is 6Eh. C language Code SMBus Device Register Reader program by Rex Chin. */ /*----- Include Header Area -----*/ #include “math.h”...
  • Page 65 Appendix delay(3000); printf(“Digital I/O pin 6,4,2,0 LED OFF ...\n”); Index 11, GPIO1x Output Data value SMB_Byte_WRITE(SMB_PORT_AD,SMB_DEVICE_ADD,0x11,0x55); delay(1500); SMB_Byte_READ(int SMPORT, int DeviceID, int REG_INDEX) outportb(SMPORT+02, 0x00); /* clear */ outportb(SMPORT+00, 0xff); /* clear */ delay(10); outportb(SMPORT+04, DeviceID+1); /* clear */ outportb(SMPORT+03, REG_INDEX); /* clear */ outportb(SMPORT+02, 0x48);...

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