Part 12: Pcie Interface - Alinx AXU2CGA User Manual

Part 12: PCIE Interface

There is a PCIE x1 slot on the AXU2CGA/B board for connecting PCIE
peripherals, and the PCIE communication speed is up to 5Gbps. PCIE signal is
directly connected to LANE0 of BANK505 PS MGT transceiver. The schematic
diagram of PCIE x 1 design is shown in Figure 12-1:
PCIE Interface ZYNQ Pin Assignment
Signal Name
PCIE_TXP
PCIE_TXN
PCIE_RXP
PCIE_RXN
PCIE_REFCLK_P
PCIE_REFCLK_N
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ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual
Figure 12-1: PCIE Schematic
Pin Name
PS_MGTTXP0_505
PS_MGTTXN0_505
PS_MGTRXP0_505
PS_MGTRXN0_505
PS_MGTREFCLK0P_505
PS_MGTREFCLK0N_505
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Pin
Number
E25 PCIE Data Transmission Positive
E26 PCIE Data Transmission Negative
F27 PCIE Data Receive Positive
F28 PCIE Data Receive Negative
F23 PCIE Data Reference Clock Positive
F24 PCIE Data Reference Clock Negative
Description