Alinx AXU2CGA User Manual page 14

The DisplayPort interface ZYNQ pin assignment is as follows:
Signal Name
GT0_DP_TX_P
GT0_DP_TX_N
GT1_DP_TX_P
GT1_DP_TX_N
505_DP_CLKP
505_DP_CLKP
DP_AUX_OUT
DP_AUX_IN
DP_OE
DP_HPD
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ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual
Figure 7-1: DP interface design Schematic
ZYNQ Pin Number
PS_MGTTXP3_505
PS_MGTTXN3_505
PS_MGTTXP2_505
PS_MGTTXN2_505
PS_MGTREFCLK2P_50
5
PS_MGTREFCLK2N_50
5
PS_MIO27
PS_MIO30
PS_MIO29
PS_MIO28
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ZYNQ Pin Description
Number
Low bits of DP Data
B23
Transmit Positive
Low bits of DP Data
B24
Transmit Negative
High bits of DP Data
C25
Transmit Positive
High bits of DP Data
C26
Transmit Negative
DP Reference Clock
C21
Positive
DP Reference Clock
C22
Negative
J15 DP Auxiliary Data Output
F16 DP Auxiliary Data Input
G16 DP Auxiliary Data Output Enable
K15 DP Insertion Signal Detection