Why Run A Ram Test; System Set Test Group; Subtests - Dell PowerEdge 4200 Installation And Troubleshooting Manual

whether the RAM read and write operations are affecting
more than one memory address location at one time. This
subtest checks all available RAM.
The Comprehensive Memory Test performs an address
check as well as the following:
•
Data pattern checks, to look for RAM bits that are
stuck high or low, short-circuited data lines, and
some data pattern problems that are internal to the
memory chips
•
A parity check that verifies the ability of the memory
subsystem to detect errors
•
A refresh check, to verify that the dynamic RAM
(DRAM) is being recharged properly
The Cache Memory Test confirms the functionality of the
computer's cache controller chip and the cache memory.

Why Run a RAM Test?

Faulty memory can cause a variety of problems that may
not, at first glance, appear to be happening in RAM. If the
computer is displaying one or more of the following
symptoms, run the subtests in the RAM Test Group to
verify that the memory is not at fault:
•
A program is not running as usual, or a proven piece
of software appears to malfunction and you
confirm that the software itself is not at fault. (You
can confirm that the software is functioning properly
by moving it to another computer and running it
there.)
•
The computer periodically locks up (becomes un-
usable and must be rebooted), especially at different
places and times in different programs.
•
You get a parity error (any error message that con-
tains the word parity) at any time during operation.
These errors are usually accompanied by a reference
to an address—the location of the portion of memory
where the error occurred—which you should record
on a copy of the Diagnostics Checklist found in
Appendix A.
•
You receive the Memory ECC fault
detected message from the Dell Hardware Instru-
mentation Package (HIP) server management
program. See Chapter 3, "Messages and Codes," for
more information on this program.
S
ystem Set Test Group
The subtests in the System Set Test Group check the
computer's basic system board components and verify
their related functions.

Subtests

The subtests that constitute the System Set Test Group
and the computer functions they confirm follow:
•
CMOS Confidence Test
Checks the NVRAM for accessibility and reliability
of data storage by performing a data pattern check
and verifying the uniqueness of memory addresses.
•
EISA Configuration Memory Test
Verifies the accessibility and reliability of the RAM
on the Extended Industry-Standard Architecture
(EISA) Configuration RAM chip, which stores the
EISA hardware configuration information. On sys-
tems without flash RAM, performs a data pattern
and address uniqueness test.
•
DMA Controller Test
Tests the direct memory access (DMA) controller
and verifies the correct operation of its page and
channel registers by writing patterns to the registers.
•
Real-Time Clock Test
Confirms the functionality and accuracy of the com-
puter's real-time clock (RTC).
•
System Timers Test
Checks the timers used by the microprocessor for
event counting, frequency generation, and other
functions. Only the functions that can be activated
by software are tested.
•
Interrupt Controller Test
Generates an interrupt on each interrupt request
(IRQ) line to verify that devices using that line can
communicate with the microprocessor and that the
interrupt controllers send the correct memory
addresses to the microprocessor.
•
Apic Test
Tests that the procedure used to boot your system is
able to properly receive interrupts from the input/
Running the System Diagnostics 5-11