Advanced Chipset Features - Boser HS-2613 Manual

Via v4 eden processor embedded engine board
Table of Contents

Advertisement

5.6

Advanced Chipset Features

This section allows you to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and
the access to the system memory resources, such as DRAM and the
external cache. It also coordinates the communications between the
conventional ISA and PCI buses. It must be stated that these items
should never be altered. The default settings have been chosen
because they provide the best operating conditions for your system.
You must consider making any changes only if you discover that the
data has been lost while using your system.
Phoenix - AwardBIOS CMOS Setup Utility
DRAM Clock/Drive Control
AGP & P2P Bridge Control
CPU & PCI Bus Control
Memory Hole
System BIOS Cacheable
Video RAM Cacheable
Init Display First
↑↓← →: Select Item
+/-/PU/PD: Value
F5: Previous Values
Phoenix - AwardBIOS CMOS Setup Utility
Current FSB Frequency
Current DRAM Frequency
DRAM Timing
X SDRAM CAS Latency [DDR/DDR
X Bank Interleave
X Precharge to Active(Trp)
X Active to Precharge(Tras)
X Active to CMD(Trcd)
X REF to ACT/REF(Trfc)
X ACT(0) to ACT(1) (TRRD)
Read to Precharge (Trtp)
Write to Read CMD (Twtr)
Write Recovery Time (Twr)
DRAM Command Rate
RDSAIT mode
X RDSAIT selection
↑↓← →: Select Item
+/-/PU/PD: Value
F5: Previous Values
50
Advanced Chipset Features
[Press Enter]
[Press Enter]
[Press Enter]
[Disabled]
[Enabled]
[Disabled]
[PCI Slot]
F10: Save
F6: Fail-Safe Defaults
DRAM Clock/Drive Control
100MHz
200MHz
[Auto By SPD]
2.5/4
Disabled
4T
07T
4T
25T
3T
[2T]
[1T/2T]
[4T]
[2T Command]
[Auto]
03
F10: Save
F6: Fail-Safe Defaults
Item Help
Esc: Quit
F1: General Help
F7: Optimized Defaults
Item Help
Esc: Quit
F1: General Help
F7: Optimized Defaults

Advertisement

Table of Contents
loading

Table of Contents