Pci Express / Sumit Connectors (J2-J3) - VersaLogic Komodo VL-EPICs-36 Reference Manual

PCI Express / SUMIT Connectors (J2-J3)

The SUMIT A and B connectors (J3 and J2, respectively) provide a subset of the PCI Express
functionality, as shown in Table 8 and Table 9. See the
description of the SUMIT interface.
J3
Pin Signal Name
1 +5VSB
3 3.3V
5 3.3V
7 EXPCD_REQ#
9 EXPCD_PRSNT#
11 USB_OC#0/1
13 USB_OC#2/3
15 +5V
17 USB3+
19 USB3-
21 +5V
23 USB2+
25 USB2-
27 +5V
29 USB1+
31 USB1-
33 +5V
35 USB0+
37 USB0-
39 GND
41 A_PETp0
43 A_PETn0
45 GND
47 PERST#
49 WAKE#
51 +5V
VL-EPICs-36 Reference Manual
Table 8: SUMIT A Connector Pinout
Function
+5V power
+3.3V power
+3.3V power
Express card request
Express card present
USB overcurrent flag 0/1
USB overcurrent flag 2/3
+5V power
USB3 data +
USB3 data –
+5V power
USB2 data +
USB2 data –
+5V power
USB1 data +
USB1 data –
+5V power
USB0 data +
USB0 data –
Ground
Link A, lane 0 transmit +
Link A, lane 0 transmit –
Ground
Reset
Wake on event signal
+5V power
Interfaces and Connectors
SUMIT Specification
J3
Pin Signal Name
2 +12V
4 SMB/I2C_DATA
6 SMB/I2C_CLK
8 SMB/I2C_ALERT#
10 SPI/uWire_DO
12 SPI/uWire_DI
14 SPI/uWire_CLK
16 SPI/uWire_CS0#
18 SPI/uWire_CS1#
20 Reserved
22 LPC_DRQ
24 LPC_AD0
26 LPC_AD1
28 LPC_AD2
30 LPC_AD3
32 LPC_FRAME#
34 SERIRQ#
36 LPC_PRSNT#/GND
38 CLK_33MHz
40 GND
42 A_PERp0
44 A_PERn0
46 APRSNT#/GND
48 A_CLKp
50 A_CLKn
52 GND
for a complete
Function
+12V power
SMBus data
SMBus clock
SMBus interrupt line in
SPI data out from master
SPI data in to master
SPI clock
SPI chip select 0
SPI chip select 1
Do not use
LPC DMA request
LPC line 0
LPC line 1
LPC line 2
LPC line 3
LPC frame
Serial IRQ legacy
LPC card present
33 MHz clock out
Ground
Link A, lane 0 receive +
Link A, lane 0 receive –
Link A card present
Link A clock +
Link A clock –
Ground
29