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SPISTATUS (READ/WRITE) CA9h (or C99h)
D7
IRQSEL1
Bit Mnemonic
D7-D6 IRQSEL
D5-D4 SPICLK
D3
HW_IRQ_EN
D2 LSBIT_1ST
D1 HW_INT
D0 BUSY
VL-EPICs-36 Reference Manual
D6 D5
IRQSEL0 SPICLK1 SPICLK0
Table 22: SPI Control Register 2 Bit assignments
Description
IRQ Select – These bits select which IRQ will be asserted when a
hardware interrupt from a connected SPI device occurs. The
HW_IRQ_EN bit must be set to enable SPI IRQ functionality.
IRQSEL1 IRQSEL0 IRQ
0 0
0 1
1 0
1 1
Note: The on-board digital I/O chips must be configured for open-drain
and mirrored interrupts in order for any SPI device to use hardware
interrupts.
SPI SCLK Frequency – These bits set the SPI clock frequency.
SPICLK1 SPICLK0 Frequency
0 0
0 1
1 0
1 1
Hardware IRQ Enable – Enables or disables the use of the selected
IRQ (IRQSEL) by an SPI device.
0 = SPI IRQ disabled, default
1 = SPI IRQ enabled
Note: The selected IRQ is shared with PC/104 ISA bus devices. CMOS
settings must be configured for the desired ISA IRQ.
SPI Shift Direction – Controls the SPI shift direction of the SPIDATA
registers. The direction can be shifted toward the least significant bit or
the most significant bit.
0 = SPIDATA data is left-shifted (MSbit first), default
1 = SPIDATA data is right-shifted (LSbit first)
SPI Device Interrupt State – This bit is a status flag that indicates
when the hardware SPX signal SINT# is asserted.
0 = Hardware interrupt on SINT# is deasserted
1 = Interrupt is present on SINT#
This bit is read-only and is cleared when the SPI device's interrupt is
cleared.
SPI Busy Flag – This bit is a status flag that indicates when an SPI
transaction is underway.
0 = SPI bus idle
1 = SCLK is clocking data in and out of the SPIDATA registers
This bit is read-only.
D4 D3 D2
HW_IRQ_EN LSBIT_1ST
IRQ3
IRQ4
IRQ5
IRQ10
1.042 MHz
2.083 MHz
4.167 MHz
8.333 MHz
Interfaces and Connectors
D1 D0
HW_INT BUSY
44