Revision Level Register - VersaLogic Komodo VL-EPICs-36 Reference Manual

Revision Level Register

REVLEV (Read Only) CA1h (or C91h)
D7
RL4
Bit Mnemonic
D7-D3 RL
D2 EXT
D1 CUSTOM
D0 REV
VL-EPICs-36 Reference Manual
D6 D5 D4
RL3 RL2 RL1
Table 26: Revision Level Register Bit Assignments
Description
FPGA Revision Level — These bits are hard-coded to represent the FPGA
revision. Contact VersaLogic Support for further information.
These bits are read-only.
Extended Temperature — Indicates operating temperature range.
0 = Standard temperature range
1 = Extended temperature range
This bit is read-only.
Custom Flag – Indicates whether this is a custom FPGA.
0 = Standard
1 = Custom
This bit is read-only.
Beta Flag — Indicates whether this is a Beta product.
0 = Standard
1 = Beta
This bit is read-only.
D3 D2 D1
RL0 EXT CUST
Special Registers
D0
BETA
49