Table 14 Pci Express Signal Descriptions (General Purpose) - Congatec COM Express conga-TCA7 User Manual

Table 14 PCI Express Signal Descriptions (General Purpose)
Signal Pin Description
PCIE_RX0+ B68 PCI Express channel 0, Receive Input differential pair
PCIE_RX0- B69
PCIE_TX0+ A68 PCI Express channel 0, Transmit Output differential pair
PCIE_TX0- A69
PCIE_RX1+ B64 PCI Express channel 1, Receive Input differential pair
PCIE_RX1- B65
PCIE_TX1+ A64 PCI Express channel 1, Transmit Output differential pair
PCIE_TX1- A65
PCIE_RX2+ B61 PCI Express channel 2, Receive Input differential pair
PCIE_RX2- B62
PCIE_TX2+ A61 PCI Express channel 2, Transmit Output differential pair
PCIE_TX2- A62
PCIE_RX3+ B58 PCI Express channel 3, Receive Input differential pair
PCIE_RX3- B59
PCIE_TX3+ A58 PCI Express channel 3, Transmit Output differential pair
PCIE_TX3- A59
PCIE_RX4+ B55 PCI Express channel 4, Receive Input differential pair
PCIE_RX4- B56
PCIE_TX4+ A55 PCI Express channel 4, Transmit Output differential pair
PCIE_TX4- A56
PCIE_RX5+ B52 PCI Express channel 5, Receive Input differential pair
PCIE_RX5- B53
PCIE_TX5+ A52 PCI Express channel 5, Transmit Output differential pair
PCIE_TX5- A53
PCIE_RX6+ C19 PCI Express channel 6, Receive Input differential pair
PCIE_RX6- C20
PCIE_TX6+ D19 PCI Express channel 6, Transmit Output differential pair
PCIE_TX6- D20
PCIE_RX7+ C22 PCI Express channel 7, Receive Input differential pair
PCIE_RX7- C23
PCIE_TX7+ D22 PCI Express channel 7, Transmit Output differential pair
PCIE_TX7- D23
PCIE_CLK_REF+ A88 PCI Express Reference Clock output for all PCI Express
PCIE_CLK_REF- A89 and PCI Express Graphics Lanes
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I/O PU/PD Comment
I PCIE Supports PCI Express Base Specification, Revision 3.0
O PCIE Supports PCI Express Base Specification, Revision 3.0
I PCIE Supports PCI Express Base Specification, Revision 3.0
O PCIE Supports PCI Express Base Specification, Revision 3.0
I PCIE Supports PCI Express Base Specification, Revision 3.0
O PCIE Supports PCI Express Base Specification, Revision 3.0
I PCIE Supports PCI Express Base Specification, Revision 3.0
O PCIE Supports PCI Express Base Specification, Revision 3.0
I PCIE Supports PCI Express Base Specification, Revision 3.0
O PCIE Supports PCI Express Base Specification, Revision 3.0
I PCIE Supports PCI Express Base Specification, Revision 3.0
O PCIE Supports PCI Express Base Specification, Revision 3.0
I PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
O PCIE
Not supported
O PCIE A PCI Express Gen2/3 compliant clock buffer chip must be
used on the carrier board if the design involves more than
one PCI Express device.
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