Controller Hardware; Watchdog Timer - ConMed Sabre 2400 Operators & Service Manual

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3.1.3 Controller Hardware

The Sabre 2400 Controller PWB Assembly is
based on the 8031, a single chip, 8-bit micropro-
cessor which utilizes external program memory.
Refer to schematic, Figure 4.2. This controller has
the following features.
1. Four 8-bit Ports (0,1,2,3) which are individu-
ally addressable as 32 Input/Output (I/O) lines.
2. Two 16-bit timer/event counters.
3. 64 K bytes of externally addressable program
memory.
4. On-chip oscillator and clock circuit which is
connected to an external 10 MHz clock signal
derived from a 20 MHz quartz time base (A2Y1).
5. 128 bytes of internal RAM used as a "scratch
pad" by the processor.
The remainder of the controller circuitry consists
of the Watchdog Timer (WDT), Power On Reset
(POR), Address Decoder, Peripheral Interface
Adapters (2x) (PIA), Base Voltage Generator
(BVG), Output Current and Line Voltage
Current Sensing Circuit, Waveform Generator
(WFG), Tone Generator, and the Aspen Return
Monitor (A.R.M.) DAC and current source.
3.1.3.1 Watchdog Timer (WDT)
The function of this circuit is to monitor the
microprocessor for a failure that would cause
unpredictable results. During normal operation,
the microprocessor program executes in a known
sequence. If a software error is detected, an inter-
nal interrupt is generated which halts the opera-
tion of the microprocessor. If there is a hardware
failure sensed by software control, program execu-
tion will again be terminated.
Should a failure occur in the CPU that prevents
the detection of a problem, thus allowing pro-
gram execution in a random manner, the Sabre
2400 is designed so that the WDT detects the
problem. The WDT shuts down the malfunction-
ing unit to minimize the effects of the failure.
This is accomplished by requiring the micropro-
cessor to write to the WDT once during each
program execution cycle. This WRITE PULSE
3-2
is referred to as the Watchdog Timer Strobe
(WDSTR). Each cycle is 25 +/- 2 milliseconds
long. The WDT circuit must hear from the
microprocessor within a 18 to 34 msec window.
If the WDSTR occurs early because the pro-
gram "skipped" a portion of the software or late
because it was "hung" in a program loop, the fol-
lowing results:
1. The circuit latches in the failed condition so
that further strobing from the microprocessor
cannot clear the previous failure.
2. An interrupt is generated which stops abnor-
mal program execution. If the microprocessor can
still respond to the interrupt, a "fatal" software
routine will execute, displaying an error code
HLP-4.
3. The interrupt signal, is used to gener-
ate WFAIL, which disables the Base Voltage
Generator and Waveform Generator, preventing
further generation of RF output.
The Watchdog Timer (WDT) is made up of a
dual, retriggerable, one-shot multivibrator (U1),
associated RC timing components (R1, C2, R2,
and C3), and associated gate (U2). The first
stage one-shot is set to time out at the minimum
WDSTR interval of 20 msec by the RC combi-
nation of R1 and C2. The trailing (falling) edge
of WDSTR triggers the first stage causing Q1
(U1-6) to go true (high) for approximately 18
msec. The rising edge of Q1 triggers the second
stage one-shot via U1-12, causing Q2 (U1-10) to
go high and /Q2 (U1-9) to go low. The 34 msec
timing of this stage is set by the RC combination
of R2 and C3. In normal operation WDT strobes
will occur after stage 1 has timed out (Q1=0) but
before stage 2 times out (Q2=1). The one-shot
is retriggerable and the rising edge of Q1 will
restart the 34 msec timing sequence in the second
stage even though it may not have completed its
current time delay. Normal operation is indicated
by (Q2) never going low.