Uart Interface - Quectel EC200T Series Hardware Design

Module
USB_DM
USB_DP
GND
A common mode choke L1 is recommended to be added in series between the module and customer's
MCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should be
added in series between the module and the test points so as to facilitate debugging, and the resistors are
not mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 components
must be placed close to the module, and also these resistors should be placed close to each other. The
extra stubs of trace must be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
It is important to route the USB signal traces as differential pairs with total grounding. The impedance

of USB differential trace is 90Ω.
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is

important to route the USB differential traces in inner layer with ground shielding on not only upper
and lower layers but also right and left sides.
 Special attention should be paid to the selection of ESD device on the USB data line. Its parasitic
capacitance should not exceed 2 pF and should be placed as close as possible to the USB interface.

3.8. UART Interface

The following table shows the pin definition of the main UART interface.
The main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps and
230400bps baud rates, and the default is 115200bps. This interface supports RTS and CTS hardware
flow control, and be used for AT command communication and data transmission.
EC200T_Series_Mini_PCIe_Hardware_Design
Minimize these stubs
R3
R4
L1
ESD Array Close to Module
Figure 6: Reference Circuit of USB Interface
LTE Standard Module Series
EC200T Series Mini PCIe Hardware Design
Test Points
NM_0R
NM_0R
MCU
USB_DM
USB_DP
GND
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