Entering Idle Mode; Exit From Idle Mode - Siemens C541U User Manual

9.1.1 Entering Idle Mode

The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE
(PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS
(PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a concurrent setting of
both bits, IDLE and IDLS, does not initiate the idle mode. Bits IDLE and IDLS will automatically be
cleared after being set. If one of these register bits is read the value that appears is 0. This double
instruction is implemented to minimize the chance of an unintentional entering of the idle mode
which would leave the watchdog timer's task of system protection without effect.
PCON is not a bit-addressable register, so the above mentioned sequence for entering the idle
mode is obtained by byte-handling instructions, as shown in the following example:
ORL PCON,#00000001B
ORL PCON,#00100000B
The instruction that sets bit IDLS is the last instruction executed before going into idle mode.
In idle mode, the USB module can be fully functional or can be switched off. If it is switched off in idle
mode the following steps must be processed before entering the idle mode :
– USB module clock is switched off by software (resetting bit UCLK in SFR DCR)
– additionally in full speed mode : USB PLL is switched off (resetting bit PCLK in SFR DCR)

9.1.2 Exit from Idle Mode

There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. This interrupt will be
serviced and normally the instruction to be executed following the RETI instruction will be the
one following the instruction that sets the bit IDLS.
– The other way to terminate the idle mode, is a hardware reset. Since the oscillator is still
running, the hardware reset must be held active only for two machine cycles for a complete
reset.
After leaving the idle mode through e.g. an interrupt with a switched-off USB module, a well defined
procedure must be executed foragain switching on the USB module :
– in full speed mode only
– USB module clock is switched on (setting bit UCLK in SFR DCR)
This switch off/on procedure assures a proper operation of the USB clock system. If the idle mode
is terminated by a hardware reset, the USB module has to be reconfigured as defined for the
hardware reset case.
Semiconductor Group
;Set bit IDLE, bit IDLS must not be set
;Set bit IDLS, bit IDLE must not be set
USB PLL is switched on (setting bit PCLK in SFR DCR) and
waiting 3 ms for PLL being locked
9-4
Power Saving Modes
C541U
1997-10-01