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7.1.2 Interrupt Request / Control Flags
The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative
transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually
generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the
flag that generated this interrupt is cleared by the hardware when the service routine is vectored too,
but only if the interrupt was transition-activated. lf the interrupt was level-activated, then the
requesting external source directly controls the request flag, rather than the on-chip hardware.
The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set
by a rollover in their respective timer/counter registers. When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware when the service routine is vectored too.
Special Function Register TCON (Address 88 H )
MSB
Bit No.
8FH
88 H
TF1
The shaded bits are not used for interrupt control.
Bit
Function
TF1
Timer 1 overflow flag
Set by hardware on timer/counter 1 overflow. Cleared by hardware when
processor vectors to interrupt routine.
TF0
Timer 0 overflow flag
Set by hardware on timer/counter 0 overflow. Cleared by hardware when
processor vectors to interrupt routine.
IE1
External interrupt 1 request flag
Set by hardware when external interrupt 1 edge is detected. Cleared by hardware
when processor vectors to interrupt routine.
IT1
External interrupt 1 level/edge trigger control flag
If IT1 = 0, low level triggered external interrupt 1 is selected.
If IT1 = 1, edge triggered mode for external interrupt 1 is selected. The bits IE1TR
and IE1TF in SFR ITCON (see section 7.4) further define which signal transition
at pin INT1 (rising and/or falling edge) generates an interrupt.
IE0
External interrupt 0 request flag
Set by hardware when external interrupt 0 edge is detected. Cleared by hardware
when processor vectors to interrupt routine.
IT0
External interrupt 0 level/edge trigger control flag
If IT0 = 0, low level triggered external interrupt 0 is selected.
If IT0 = 1, edge triggered mode for external interrupt 0 is selected. The bits IE0TR
and IE0TF in SFR ITCON (see section 7.4) further define which signal transition
at pin INT0 (rising and/or falling edge) generates an interrupt.
Semiconductor Group
8EH
8DH
8CH
TR1
TF0
TR0
8BH
8AH
IE1
IT1
7-10
Interrupt System
Reset Value : 00 H
LSB
89H
88H
IE0
IT0
TCON
1997-10-01
C541U
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