Ssc Port Pins Of Port 1 - Siemens C541U User Manual

6.1.1.2

SSC Port Pins of Port 1

The port pins of the SSC interface are located as alternate functions at four lines of port 4 :
– P1.2/SCLK : when used as SSC clock output, pin becomes a true push-pull output
– P1.3/SRI : when used as SSC receiver input, pin becomes an input without pullups.
– P1.4/STO : when used as SSC transmitter output, pin becomes a true push-pull output with
tristate capability
– P1.5/SLS : when used as SSC slave select input, pin directly controls the tristate condition
of P4.3
The modified port structure is illustrated in figures 6-4 and 6-5.
=1
Q
Tristate
Input Data (Read Pin)
Figure 6-4
Driver Circuit of Port 1 pins P1.2 and P1.4 (when used for SLCK and STO)
Pin Control for P1.2/SCLK
When the SSC is disabled, both Enable Push-pull and Tristate will be inactive, the pin behaves like
a standard I/O pin. In master mode and with SSC enabled, Enable Push-pull will be active and
Tristate will be inactive. In slave mode and with SSC enabled, Enable Push-pull will be inactive and
Tristate will be active.
Pin Control for P1.4/STO
When the SSC is disabled, both Enable Push-pull and Tristate will be inactive. In master mode and
SSC enabled, Enable Push-pull will be active and Tristate will be inactive. In slave mode and SSC
enabled, Enable Push-pull will be active. If the transmitter is enabled (SLS and TEN active), Tristate
will be inactive. If the transmitter is disabled (either SLS or TEN inactive), Tristate will be active.
Semiconductor Group
Delay = 1 State
Enable Push-pull
&
_ 1 <
On-Chip Peripheral Components
<
_
1
p1
_ 1 <
&
n1
V
SS
=1
6-6
C541U
V
CC
p2 p3
1 < _
=1
MCS02432
1999-04-01
Port
Pin