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7.1
Interrupt Registers
7.1.1 Interrupt Enable Registers
Each interrupt vector can be individually enabled or disabled by setting or clearing the
corresponding bit in the interrupt enable registers IEN0 or IEN1. Register IEN0 also contains the
global disable bit (EA), which can be cleared to disable all interrupts at once. The SSC and USB
interrupts sources have further enable bits for individual interrupt control. Such interrupt enable bits
are controlled by specific bits in the SFRs of the corresponding peripheral units.
The IEN0 register contains the general enable/disable flags of the external interrupts 0 and 1 as well
as the timer interrupts. The SSC interrupt and the two USB interrupts are enabled/disabled by bits
in the IEN1 register. After reset the enable bits of IEN0 and IEN1 are set to 0. That means that the
corresponding interrupts are disabled.
Special Function Registers IEN0 (Address A8 H )
Bit No.
MSB
AF H
A8 H
EA
Bit
EA
–
ET1
EX1
ET0
EX0
Semiconductor Group
AE H
AD H
–
–
Function
Enable/disable all Interrupts
If EA=0, no interrupt will be acknowledged.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
Not implemented. Reserved for future use.
Timer 1 overflow interrupt enable
If ET1 = 0, the timer 1 interrupt is disabled
If ET1 = 1, the timer 1 interrupt is enabled.
External interrupt 1 enable
If EX1 = 0, the external interrupt 1 is disabled.
If EX1 = 1, the external interrupt 1 is enabled.
Timer 0 overflow interrupt enable
If ET0 = 0, the timer 0 interrupt is disabled
If ET0 = 1, the timer 0 interrupt is enabled.
External interrupt 0 enable
If EX0 = 0, the external interrupt 0 is disabled.
If EX0 = 1, the external interrupt 0 is enabled.
AC H
AB H
AA H
–
ET1
EX1
7-4
Interrupt System
C541U
Reset Value : 0XXX0000 B
LSB
A9 H
A8 H
IEN0
ET0
EX0
1997-10-01
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