Entering Power Down Mode - Siemens C541U User Manual

9.2.1 Entering Power Down Mode

The power down mode is entered by two consecutive instructions. The first instruction has to set the
flag bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the
start bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a
concurrent setting of both bits, PDE and PDS, does not initiate the power down mode. Bits PDE and
PDS will automatically be cleared after having been set and the value shown by reading one of
these bits is always 0. This double instruction is implemented to minimize the chance of
unintentionally entering the power down mode which could possibly "freeze" the chip's activity in an
undesired status. Important : the USB module must be switched off from the system clock prior to
enabling the power down mode by software :
PCON is not a bit-addressable register, so the above mentioned sequence for entering the power-
down mode is obtained by byte-handling instructions, as shown in the following example:
ANL DCR,#11111101B
ANL DCR,#11111110B
ORL PCON,#00000010B
ORL PCON,#01000000B
The instruction that sets bit PDS is the last instruction executed before going into power down
mode. When the double instruction sequence shown above is used and when bit EWPD in SFR
PCON1 is 0, the power down mode can only be left by a reset operation.
If the wake-up from power down capability is required, its function must be enabled prior to
executing the double instruction sequence shown above.
ORL SYSCON,#00010000B
ORL PCON1,#80H
ANL SYSCON,#11101111B
Note :Before entering the power down mode, the port latch of SFR P3.2 (P3.2/INT0 pin) should
contain a "1" (pin operates as input). Otherwise, the wake-up sequence discussed in the next
chapter will be started immediately when power down mode is entered.
If the wake-up from software power down mode through USB bus capability is selected, the USB
receiver must be enabled in order to detect any activity on the USB bus lines. Therefore, bit RPWD
in the USB device power down register DPWDR must be cleared before enering software power
down mode.
The USB module enters the suspend state when it detects no activity on the USB bus for more than
6 ms.
Semiconductor Group
;clear bit UCLK; USB clock is switched off
;clear bit PCLK, stop PLL (required only in full speed mode)
;set bit PDE, bit PDS must not be set
;set bit PDS, bit PDE must not be set, enter power-down
;set RMAP
;enable wake-up from power-down by setting EWPD
;80H = wake-up through pin P3.2/INT0
;90H = wake-up through USB bus
;reset RMAP (for future SFR accesses)
9-6
Power Saving Modes
C541U
1997-10-01