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Circuit Diagrams and PWB Layouts
Small Signal Board: Dolby Digital Decoder
1
2
DOLBY DIGITAL DECODER
A
A1
A4
2 V / div DC
2 V / div DC
250ns / div
1µs / div
B
A2
A5
2 V / div DC
1 V / div DC
50ns / div
2µs / div
A3
A6
C
2 V / div DC
1 V / div DC
1µs / div
5µs / div
+5M
D
2AE4
100n
7A31
BC847BW
B14b
2AE8
3A84
SPDIF-OUT
1V7
IA74
68R
100n
E
B6c
I2S-DD-CLK
B6c
I2S-DD-WS
B6c
I2S-DD-OUT
F
8204 000 8286.3
1
2
EM6E AB
7.
3
4
A7
5A39
+5M
1 V / div DC
30R
200ns / div
A8
7A30
MAS3528E
1 V / div DC
100ns / div
18
PI4
24
PI8
28
PI12
29
PI13
30
SID_PI14
31
SII_PI15
32
SIC_PI16
33
PI17
DOLBY DIGITAL
34
PI18
35
PI19
MPEG-1 LAYER-2
2AC4
A1
41
_RTW
AUDIO DECODER
2AC5
IA73
2AE6
10p
42
_RTR
2V4
2AC6
100n
10p
43 _EOD
10p
2AC7
44
SYNC
10p
17
SPDIFOUT
A2
A3
25
SOC
26
SOI
27
SOD
14
SOD1
A4
15
SOD2
16
SOD3
13
CLKO
3
4
75
5
6
5A40
+5M
30R
5A41
+5M
30R
23
8
2
3A81
SID
21
100R
SII
20
SIC
19
IA71
AND
_PCS
36
37
PR
2AE5
SPREF
39
3V1
10n
38
SPDI_1
2AF0
IA75
SPDI_2
40
10n
XTI
9
XTO
10
A8
TE
6
_POR
5
4V9
SCL
4
SDA
3
12
11
22
7
1
5
6
7
8
9A38
5A38
+5M
+5V
30R
2AF3
A5
A6
I2S-BO-IN
3A82
A7
I2S-BO-WS
100R
3A83
I2S-BO-CLK
100R
+5M
2AE3
10n
IA72
SPDIF-IN1
3A74
75R
SPDIF-BO-OUT
3A77
75R
SYS-CLK1
SYS-RESET-MAS
SCL-F-DD
SDA-F-DD
7
8
9
2AC1 B4
2AC2 B5
2AC3 B5
2AC4 D4
2AC5 D4
2AC6 D4
2AC7 E4
A
2AD0 B6
2AD1 B6
2AD3 B4
2AD4 B6
2AD5 B5
2AD6 B6
2AE2 D8
2AE3 D7
2AE4 D2
B
2AE5 D7
2AE6 D3
2AE8 D2
2AF0 D6
2AF3 C8
2AF4 C7
3A72 D2
3A73 D3
3A74 D7
C
3A75 E3
3A76 E3
B1
3A77 E7
3A78 E2
B1
3A81 C7
B1
3A82 C7
3A83 D8
3A84 E2
5A38 B8
5A39 B4
D
5A40 A6
B14d
5A41 B6
7A30 B4
7A31 D2
B14b
9A38 B8
IA71 D7
IA72 D7
B6b
IA73 D3
IA74 E2
E
IA75 D7
B6a
F
CL 36532008_038.eps
070503
9
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