Table of Contents
Advertisement
Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.13.4 Diagram B14C, M61323 (IC7I42)
PIN CONFIGURATION(TOP VIEW)
Vcc1 (R)
1
Input1 (R)
2
3
Vcc1 (G)
Input1 (G)
4
Vcc1 (B)
5
Input1 (B)
6
Input1 (H)
7
Input1 (V)
8
9
GND1
Input2 (R)
10
PowerSave SW
11
Input2(G)
12
13
Input SW
Input2 (B)
14
Input2 (H)
15
Input2 (V)
16
OUTLINE:32P4B
BLOCK DIAGRAM ( M61323SP )
VCC(R)
OUTPUT(R)
32
31
Vcc(R)
R
Vcc(R)
2
1
INPUT1(R)
Vcc(R)
VCC2 (R)
32
31
OUTPUT (R)
30
GND2(R)
Vcc2(G)
29
28
OUTPUT(G)
27
GND2 (G)
26
Vcc2 (B)
25
OUTPUT(B)
24
GND2(B)
23
G Buffer out
Sync SEP in
22
Sync SEP out
21
Vcc3
20
OUTPUT(H)
19
18
OUTPUT(V)
GND3
17
OUTPUT(G)
VCC(B)
GND
VCC(G)
GND
30
29
28
27
Vcc(G)
Vcc(B)
G
Vcc(G)
Vcc(B)
3
4
5
6
INPUT1(G)
INPUT1(B)
Vcc(G)
Vcc(B)
INPUT1(H)
Figure 9-39 Internal Block Diagram and Pin Layout
PIN CONFIGURATION(TOP VIEW)
Vcc1 (R)
Input1 (R)
Vcc1 (G)
Input1 (G)
Vcc1 (B)
Input1 (B)
Input1 (H)
Input1 (V)
GND1
GND1
Input2 (R)
PowerSave SW
Input2(G)
Input SW
Input2 (B)
Input2 (H)
Input2 (V)
NC
GND
Sync-Sep.INPUT
OUTPUT
OUTPUT(B)
(G-Buffer)
26
25
24
23
Sync-Sep.
B
G
POWER
SAVE SW
GND
7
8
9
10
INPUT1(V)
INPUT2(R)
GND
POWER SAVE SW
EM6E AB
1
VCC2 (R)
36
2
OUTPUT (R)
35
3
34
GND2(R)
4
33
Vcc2(G)
5
OUTPUT(G)
32
6
GND2 (G)
31
7
30
Vcc2 (B)
8
29
OUTPUT(B)
9
28
GND2(B)
10
27
G Buffer out
11
26
Sync SEP in
12
25
NC
13
24
Sync SEP out
14
23
Vcc3
15
22
Vcc3
16
21
OUTPUT(H)
17
20
OUTPUT(V)
18
19
GND3
OUTLINE:36P2R
VCC
OUTPUT(V)
OUTPUT(H)
Sync-Sep.OUT
22
21
20
18
19
Vcc
H
V
15
12
13
14
11
INPUT2(G)
INPUT2(B)
INPUT SW
INPUT2(H)
CL 36532008_145.eps
9.
EN 175
GND
17
16
INPUT2(V)
090503
Advertisement
Table of Contents
